Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test

dc.citation.epage	256	en_US
dc.citation.spage	253	en_US
dc.contributor.author	Yen, Cheng-Cheng	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:12:38Z
dc.date.available	2014-12-08T15:12:38Z
dc.date.issued	2007	en_US
dc.description.abstract	The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-mu m CMOS technology.	en_US
dc.identifier.isbn	978-1-4244-1014-9	en_US
dc.identifier.journal	IPFA 2007: PROCEEDINGS OF THE 14TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/9701
dc.identifier.wosnumber	WOS:000251130700048
dc.language.iso	en_US	en_US
dc.title	Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test	en_US
dc.type	Proceedings Paper	en_US

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