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用於軟體無線電基頻處理之系統晶片設計技術-子計畫三:數位訊號處理器與可重置加速器之設計(III)

dc.contributor.author劉志尉en_US
dc.contributor.authorChih-WeiLiuen_US
dc.contributor.department交通大學電子工程系zh_TW
dc.date.accessioned2014-12-13T10:31:28Z
dc.date.available2014-12-13T10:31:28Z
dc.date.issued2004en_US
dc.description.sponsorship行政院國家科學委員會zh_TW
dc.identifier.govdocNSC93-2220-E009-034zh_TW
dc.identifier.urihttps://www.grb.gov.tw/search/planDetail?id=1031005&docId=196439en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/90958
dc.language.isozh_TWen_US
dc.title用於軟體無線電基頻處理之系統晶片設計技術-子計畫三:數位訊號處理器與可重置加速器之設計(III)zh_TW
dc.titleThe Design of DSP Processor Core and Configurable Accelerator(III)en_US
dc.typePlanen_US

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