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A Reliable Brain Computer Interface Implemented on an FPGA for a Mobile Dialing System

dc.citation.epage657en_US
dc.citation.spage654en_US
dc.citation.woscount0en_US
dc.contributor.authorFeng, Chih-Weien_US
dc.contributor.authorHu, Ting-Kueien_US
dc.contributor.authorChang, Jui-Chungen_US
dc.contributor.authorFang, Wai-Chien_US
dc.contributor.department電子工程學系及電子研究所zh_TW
dc.contributor.departmentDepartment of Electronics Engineering and Institute of Electronicsen_US
dc.date.accessioned2015-07-21T08:31:30Z
dc.date.available2015-07-21T08:31:30Z
dc.date.issued2014-01-01en_US
dc.description.abstractThis paper demonstrates a high performance brain-computer interface (BCI) that allows users to dial phone numbers. The system is based on Canonical Correlation Analysis (CCA) and Steady-State Visual Evoked Potential (SSVEP). Through six frequency bands (9Hz, 10Hz, 11Hz, 12Hz, 13 Hz, 14Hz) displayed on the screen, subjects can choose a phone number by gazing at the display interface. This proposed EEG system has been implemented in Field-Programmable Gate Arrays (FPGA), and shows high accuracy, high integration density, and low cost. These features are meaningful for implementing a real-time SSVEP-based BCI.en_US
dc.identifier.isbn978-1-4799-3432-4en_US
dc.identifier.issn0271-4302en_US
dc.identifier.journal2014 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS)en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/124895
dc.identifier.wosnumberWOS:000346488600168en_US
dc.language.isoen_USen_US
dc.titleA Reliable Brain Computer Interface Implemented on an FPGA for a Mobile Dialing Systemen_US
dc.typeProceedings Paperen_US

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