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A VLSI architecture design for dual-mode QAM and VSB digital CATV transceiver

dc.citation.epage2356en_US
dc.citation.issue12en_US
dc.citation.spage2351en_US
dc.citation.volumeE81Ben_US
dc.contributor.authorShiue, MTen_US
dc.contributor.authorWang, CKen_US
dc.contributor.authorWay, WIen_US
dc.contributor.department電信工程研究所zh_TW
dc.contributor.departmentInstitute of Communications Engineeringen_US
dc.date.accessioned2014-12-08T15:47:14Z
dc.date.available2014-12-08T15:47:14Z
dc.date.issued1998-12-01en_US
dc.description.abstractIn this paper, a transceiver VLSI architecture is proposed for high speed digital CATV modems, which can perform both the QAM and the VSB transmissions [1], [2]. The proposed architecture of all-digital dual-mode QAM/VSB receiver consists of digital AGC, digital demodulator, fractionally spaced blind equalizer and DFE, digital carrier recovery, and symbol timing recovery. Finite word-length simulation results show that the proposed architecture can achieve an SNR 29 dB for both the 64-QAM mode and 8-VSB mode when the 10 bit ADC input signal SNR is 36 dB, and there are +/-6 kHz of carrier frequency offset, +/- 110 ppm of symbol rate offset, and -82 dBc carrier phase-jitter at 10 kHz away from the nominal carrier frequency.en_US
dc.identifier.issn0916-8516en_US
dc.identifier.journalIEICE TRANSACTIONS ON COMMUNICATIONSen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/31690
dc.identifier.wosnumberWOS:000077770300014
dc.language.isoen_USen_US
dc.subjectQAMen_US
dc.subjectVSBen_US
dc.subjectAGCen_US
dc.subjectcarrier recoveryen_US
dc.subjecttiming recoveryen_US
dc.subjectfractionally spaced blind equalizer and DFEen_US
dc.titleA VLSI architecture design for dual-mode QAM and VSB digital CATV transceiveren_US
dc.typeArticle; Proceedings Paperen_US

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