Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability

dc.citation.epage	39	en_US
dc.citation.spage	36	en_US
dc.contributor.author	Ker, Ming-Dou	en_US
dc.contributor.author	Hu, Fang-Ling	en_US
dc.contributor.department	電機學院	zh_TW
dc.contributor.department	College of Electrical and Computer Engineering	en_US
dc.date.accessioned	2014-12-08T15:16:38Z
dc.date.available	2014-12-08T15:16:38Z
dc.date.issued	2007	en_US
dc.description.abstract	A new circuit design for mixed-voltage I/O buffers to prevent hot-carrier degradation is proposed. The mixed-voltage (2xVDD tolerant) I/O buffer is designed with hot-carrier-prevented circuits in a 0.18-mu m CMOS process to receive 3.3-V (2xVDD tolerant) input signals without suffering gate-oxide reliability, circuit leakage issues, and hot-carrier degradation. In the experimental chip, the proposed mixed-voltage I/O buffer can be operated with signal speed of up to 266 MHz, which can fully meet the applications of PCI-X 2.0.	en_US
dc.identifier.isbn	978-1-4244-0582-4	en_US
dc.identifier.journal	2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/12279
dc.identifier.wosnumber	WOS:000247000000009
dc.language.iso	en_US	en_US
dc.title	Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability	en_US
dc.type	Proceedings Paper	en_US

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