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Reliability Analysis of Amorphous Silicon Thin-Film Transistors during Accelerated ESD Stress

dc.citation.epage289en_US
dc.citation.spage286en_US
dc.citation.woscount0en_US
dc.contributor.authorTsai, Jung-Rueyen_US
dc.contributor.authorWen, Ting-Tingen_US
dc.contributor.authorYang, Shao-Mingen_US
dc.contributor.authorSheu, Geneen_US
dc.contributor.authorChang, Ruey-Daren_US
dc.contributor.authorSyu, Yi-Jhenen_US
dc.contributor.authorLiu, Chin-Pingen_US
dc.contributor.authorChang, Hsiu-Fuen_US
dc.contributor.authorWei, Zhao-Huien_US
dc.contributor.department奈米中心zh_TW
dc.contributor.departmentNano Facility Centeren_US
dc.date.accessioned2017-04-21T06:49:47Z
dc.date.available2017-04-21T06:49:47Z
dc.date.issued2015en_US
dc.description.abstractThis work investigates the degradation of electrical characteristics of amorphous silicon thin-film transistors during the accelerated ESD stress with a 40V high voltage and a high/low current of 2 mA/0.1 mu A conditions. Both the leakage current and the threshold voltage shift are severe as the accelerated ESD stress applied at the gate region. The 40V accelerated ESD stress with a high current has more severe impact on the electrical performance of device than that with a low current.en_US
dc.identifier.isbn978-1-4799-9928-6en_US
dc.identifier.issn1946-1550en_US
dc.identifier.journalPROCEEDINGS OF THE 22ND INTERNATIONAL SYMPOSIUM ON THE PHYSICAL AND FAILURE ANALYSIS OF INTEGRATED CIRCUITS (IPFA 2015)en_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/136101
dc.identifier.wosnumberWOS:000380466200073en_US
dc.language.isoen_USen_US
dc.titleReliability Analysis of Amorphous Silicon Thin-Film Transistors during Accelerated ESD Stressen_US
dc.typeProceedings Paperen_US

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