A 0.6V, 1.3GHZ DYNAMIC COMPARATOR WITH CROSS-COUPLED LATCHES

dc.citation.woscount	0	en_US
dc.contributor.author	Kuo, Bo-Jyun	en_US
dc.contributor.author	Chen, Bo-Wei	en_US
dc.contributor.author	Tsai, Chia-Ming	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.date.accessioned	2017-04-21T06:48:28Z
dc.date.available	2017-04-21T06:48:28Z
dc.date.issued	2015	en_US
dc.description.abstract	This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=10(-9), the comparator achieves 143fJ at 3.3GHz and a 0.9V supply, which decreases to only 49fJ at 1.3GHz and a 0.6V supply. Both measured results are based on the input differential voltage of only 4.2mV. The comparator is implemented in 65nm CMOS technology and the chip area of the core circuit occupies 265 mu m(2).	en_US
dc.identifier.isbn	978-1-4799-6275-4	en_US
dc.identifier.journal	2015 International symposium on VLSI Design, Automation and Test (VLSI-DAT)	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/136075
dc.identifier.wosnumber	WOS:000380584400030	en_US
dc.language.iso	en_US	en_US
dc.title	A 0.6V, 1.3GHZ DYNAMIC COMPARATOR WITH CROSS-COUPLED LATCHES	en_US
dc.type	Proceedings Paper	en_US

Files

Now showing 1 - 1 of 1