Accelerating Manycore Simulation by Efficient NoC Interconnection Partition on FPGA Simulation Platform
| dc.citation.epage | 319 | en_US |
| dc.citation.spage | 316 | en_US |
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Ku, Wei-Chun | en_US |
| dc.contributor.author | Chen, Tien-Fu | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.date.accessioned | 2017-04-21T06:50:05Z | |
| dc.date.available | 2017-04-21T06:50:05Z | |
| dc.date.issued | 2011 | en_US |
| dc.description.abstract | manycore architecture is the trend of system design. However, manycore simulators face the important issue than general multicore simulators is simulation speed. Several studies provide a FPGA simulation methodology to solve it, but they almost do it by providing a new internal design of core. And some of them don\'t care the correctness without interconnection simulation. This paper provides a PVCT module and NIP methodology to solve these two issues. According to our experiment, we could provide a 91.4 MIPS simulation performance averagely with Splash2 benchmark by three physical cores. The number of three is decided by capability of Xilinx XC2V8000 FPGA chip. | en_US |
| dc.identifier.isbn | 978-1-4244-8499-7 | en_US |
| dc.identifier.journal | 2011 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT) | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/134795 | |
| dc.identifier.wosnumber | WOS:000300488600069 | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | Accelerating Manycore Simulation by Efficient NoC Interconnection Partition on FPGA Simulation Platform | en_US |
| dc.type | Proceedings Paper | en_US |
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