Different approaches for reliability enhancement of p-channel flash memory
| dc.citation.epage | 642 | en_US |
| dc.citation.spage | 641 | en_US |
| dc.contributor.author | Chung, SS | en_US |
| dc.contributor.author | Chen, YJ | en_US |
| dc.contributor.author | Tsai, AW | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:25:47Z | |
| dc.date.available | 2014-12-08T15:25:47Z | |
| dc.date.issued | 2004 | en_US |
| dc.description.abstract | In this paper, we will demonstrate two different strategies for designing p-channel flash memories, for achieving better reliability, in particular data retention and drain-disturb. The first one is by using a gate-engineering approach and the other one is using a newly developed substrate bias enhanced Avalanche Hot Electron (ABE) injection programming scheme. For the former, a p-doped floating gate on both p-channel flash cells can be achieved with superior data retention characteristics as well as a 3-order improvement of the drain disturb. For the latter, it exhibits much higher speed and much lower voltage for programming, and very good drain disturb characteristics. | en_US |
| dc.identifier.doi | 10.1109/RELPHY.2004.1315429 | en_US |
| dc.identifier.isbn | 0-7803-8315-X | en_US |
| dc.identifier.journal | 2004 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM PROCEEDINGS | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/RELPHY.2004.1315429 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/18212 | |
| dc.identifier.wosnumber | WOS:000222139900138 | |
| dc.language.iso | en_US | en_US |
| dc.title | Different approaches for reliability enhancement of p-channel flash memory | en_US |
| dc.type | Proceedings Paper | en_US |