Method for Resolving Simultaneous Same-Row Access In Dual-Port 8T SRAM with Asynchronous Dual-Clock Operation

Abstract

This work proposes a novel Dual-Port (DP) 8T SRAM operation scheme. The scheme improves the Read stability and Write-ability, and allows asynchronous operation with arbitrary clock timing skew between two ports. It facilitates high performance, low-power and low VM1N with minimum device and area overhead. Postsimulation results show almost no timing penalty for simultaneous same-row access and the performance is almost the same as that for one port operation.