Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process

Abstract

Different electrostatic discharge (ESD) devices in a 0.35-mum silicon germanium (SiGe) RF BiCMOS process are characterized in detail by transmission line pulse (TLP) generator and ESD simulator for on-chip ESD protection design. The test structures of diodes with different p-n junctions and the silicon-germanium heterojunction bipolar transistors (HBTs) with different layout parameters have been drawn for investigating their ESD robustness. The human-body-model (HBM) ESD robustness of SiGe HBTs with the optional low-voltage (LV), ligh-voltage (HV), and high-speed (HS) implantations has been measured and compared in the experimental test chips.