Basic hardware module for a nonlinear programming algorithm and applications
| dc.citation.epage | 1586 | en_US |
| dc.citation.issue | 8 | en_US |
| dc.citation.spage | 1579 | en_US |
| dc.citation.volume | 33 | en_US |
| dc.contributor.author | Lin, SY | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | 電控工程研究所 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.contributor.department | Institute of Electrical and Control Engineering | en_US |
| dc.date.accessioned | 2014-12-08T15:01:35Z | |
| dc.date.available | 2014-12-08T15:01:35Z | |
| dc.date.issued | 1997-08-01 | en_US |
| dc.description.abstract | We present a VLSI-array-processor architecture for the implementation of a nonlinear programming algorithm that solves discrete-time optimal control problems for nonlinear systems with control constraints. We incorporate this hardware module with a two-phase parallel computing method and develop a VLSI-array-processor architecture to implement a receding horizon controller for constrained nonlinear systems. On the basis of current VLSI technologies, the estimated computing time to obtain the receding-horizon feedback-control solution meets the realtime processing-system needs. (C) 1997 Elsevier Science Ltd. | en_US |
| dc.identifier.issn | 0005-1098 | en_US |
| dc.identifier.journal | AUTOMATICA | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/422 | |
| dc.identifier.wosnumber | WOS:A1997XU55600015 | |
| dc.language.iso | en_US | en_US |
| dc.subject | nonlinear programming | en_US |
| dc.subject | optimal control | en_US |
| dc.subject | nonlinear systems | en_US |
| dc.subject | nonlinear control | en_US |
| dc.subject | implementations | en_US |
| dc.subject | integrated circuits | en_US |
| dc.title | Basic hardware module for a nonlinear programming algorithm and applications | en_US |
| dc.type | Article; Proceedings Paper | en_US |