Buffer size optimization for full-search block matching algorithms

dc.citation.epage	85	en_US
dc.citation.spage	76	en_US
dc.contributor.author	Yeh, YH	en_US
dc.contributor.author	Lee, CY	en_US
dc.contributor.department	交大名義發表	zh_TW
dc.contributor.department	電子工程學系及電子研究所	zh_TW
dc.contributor.department	National Chiao Tung University	en_US
dc.contributor.department	Department of Electronics Engineering and Institute of Electronics	en_US
dc.date.accessioned	2014-12-08T15:27:26Z
dc.date.available	2014-12-08T15:27:26Z
dc.date.issued	1997	en_US
dc.description.abstract	This paper presents how to find optimized buffer size for VLSI architectures of full-search block matching algorithms. Starting from the DG (dependency graph) analysis, we focus in the problem of reducing the internal buffer size under minimal I/O bandwidth constraint As a result a systematic design procedure for buffer optimization is derived to reduce realization cost.	en_US
dc.identifier.isbn	0-8186-7958-1	en_US
dc.identifier.issn	1063-6862	en_US
dc.identifier.journal	IEEE INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS	en_US
dc.identifier.uri	https://ir.lib.nycu.edu.tw/handle/11536/19699
dc.identifier.wosnumber	WOS:A1997BJ33Y00008
dc.language.iso	en_US	en_US
dc.title	Buffer size optimization for full-search block matching algorithms	en_US
dc.type	Proceedings Paper	en_US

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