A 794Mbps 135mW Iterative Detection and Decoding Receiver for 4x4 LDPC-Coded MIMO Systems in 40nm
| dc.citation.woscount | 0 | en_US |
| dc.contributor.author | Wu, Wei-Hsuan | en_US |
| dc.contributor.author | Sun, Wei-Cheng | en_US |
| dc.contributor.author | Yang, Chia-Hsiang | en_US |
| dc.contributor.author | Ueng, Yeong-Luh | en_US |
| dc.contributor.department | 交大名義發表 | zh_TW |
| dc.contributor.department | National Chiao Tung University | en_US |
| dc.date.accessioned | 2017-04-21T06:49:12Z | |
| dc.date.available | 2017-04-21T06:49:12Z | |
| dc.date.issued | 2015 | en_US |
| dc.description.abstract | A low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems with iterative detection and decoding (IDD) chip is integrated in 1.33mm(2) in 40nm CMOS. The maximum gross throughput is 794Mb/s for a 4x4 16-QAM configuration at 288MHz. The chip dissipates 135mW at 0.9V, achieving an energy efficiency of 170pJ/bit. Compared to non-IDD receivers, composed of state-of-the art MIMO detectors and LDPC decoders, this work achieves even higher area and energy efficiencies, despite the improved error performance. | en_US |
| dc.identifier.isbn | 978-4-86348-502-0 | en_US |
| dc.identifier.journal | 2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS) | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/135885 | |
| dc.identifier.wosnumber | WOS:000370961400034 | en_US |
| dc.language.iso | en_US | en_US |
| dc.title | A 794Mbps 135mW Iterative Detection and Decoding Receiver for 4x4 LDPC-Coded MIMO Systems in 40nm | en_US |
| dc.type | Proceedings Paper | en_US |
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