Power gating technique for embedded pseudo SRAM
| dc.citation.epage | 263 | en_US |
| dc.citation.spage | 260 | en_US |
| dc.contributor.author | Cheng, Ching-Yun | en_US |
| dc.contributor.author | Chang, Ming-Hung | en_US |
| dc.contributor.author | Hwang, Wei | en_US |
| dc.contributor.department | 電子工程學系及電子研究所 | zh_TW |
| dc.contributor.department | Department of Electronics Engineering and Institute of Electronics | en_US |
| dc.date.accessioned | 2014-12-08T15:16:36Z | |
| dc.date.available | 2014-12-08T15:16:36Z | |
| dc.date.issued | 2007 | en_US |
| dc.description.abstract | In this paper, we deploy power gating technique on a lowpower Pseudo SRAM circuit with 3TID gain cell. A 256word x 32-BL-pair 3TID gain cell array is implemented in standard logic technology with TSMC 0. l3urn model f6r multi-bank Pseudo SRAM. Each Pseudo SRAM has its independent access control unit, enabling parallel refresh and read-write accesses to different bank. By employing power gating technique in sense amplifier of 3TID gain cell array, 15% standby leakage current during sleep mode could be reduced. Also, 12% sensing speed could be enhanced when Pseudo SRAM is operated in normal mode (simulated with TSMC I 00nm technology model). | en_US |
| dc.identifier.doi | 10.1109/ICICIC.2007.522 | en_US |
| dc.identifier.isbn | 978-1-4244-0582-4 | en_US |
| dc.identifier.journal | 2007 International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers | en_US |
| dc.identifier.uri | http://dx.doi.org/10.1109/ICICIC.2007.522 | en_US |
| dc.identifier.uri | https://ir.lib.nycu.edu.tw/handle/11536/12257 | |
| dc.identifier.wosnumber | WOS:000247000000065 | |
| dc.language.iso | en_US | en_US |
| dc.title | Power gating technique for embedded pseudo SRAM | en_US |
| dc.type | Proceedings Paper | en_US |