Accurate Performance Evaluation of HEMT Devices for High-Speed Logic Applications through Rigorous Device Modelling Technique

Abstract

Tremendous progress has been made recently in the research of novel nanotechnology for future nano-electronic applications. Among all the possible technologies, III-V FETs particularly the heterostructure High Electron Mobility Transistors (HEMT) have demonstrated promising results to be the future device technology for high-speed logic applications. Precise evaluation of the delay performance for HEMT requires highly accurate intrinsic device models extracted from available measurements. In this paper, a rigorous device modelling technique based on 3-D full wave electromagnetic analysis of the device structure is presented. This technique is efficient and accurate, and the determined equivalent circuit model fits the measured S-parameter very well within the frequency range of interest.