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Design of power-aware multiplier with graceful quality-power trade-offs

dc.citation.epage1645en_US
dc.citation.spage1642en_US
dc.contributor.authorYen, JHen_US
dc.contributor.authorDung, LRen_US
dc.contributor.authorShen, CYen_US
dc.contributor.department電控工程研究所zh_TW
dc.contributor.departmentInstitute of Electrical and Control Engineeringen_US
dc.date.accessioned2014-12-08T15:25:23Z
dc.date.available2014-12-08T15:25:23Z
dc.date.issued2005en_US
dc.description.abstractA novel lossy power-aware multiplier design is studied and implemented based on the trade-off between power consumption and product precision. The power awareness of the proposed multiplier is defined as the ratio of normalized SNR and normalized power consumption under the same truncation scheme in order to reveal the trade-off efficiency between power and precision. A power-aware multiplier can carry out multiplications with different precisions under different power limitations. Configurations with high power awareness measurements can be chosen as candidates of power modes and applied to different conditions regarded to the energy limitations. A pipelined Dadda multiplier with controllable input and output precision is implemented for the purpose. The simulation shows that the power-aware design achieves higher trade-off efficiency subject to user-defined quality constraint than full precision multiplication.en_US
dc.identifier.isbn0-7803-8834-8en_US
dc.identifier.issn0271-4302en_US
dc.identifier.journal2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGSen_US
dc.identifier.urihttps://ir.lib.nycu.edu.tw/handle/11536/17763
dc.identifier.wosnumberWOS:000232002401199
dc.language.isoen_USen_US
dc.titleDesign of power-aware multiplier with graceful quality-power trade-offsen_US
dc.typeProceedings Paperen_US

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