1. 目前位置：
莊紹勳

莊紹勳 Chung, Steve S.

電子郵件／E-mail：schung@cc.nctu.edu.tw

服務單位／Department：電機學院 ／ 電子工程學系及電子研究所

著作期間／Publish Period：1984 - 2014-05-19

著作統計／Statistics

Article（26）
Patents（2）
Plan（39）
Proceedings Paper（38）
Thesis（83）

Article

序號
No.		 標題
Title		 著作日期
Date
1 The understanding of the drain-current fluctuation in a silicon-carbon source-drain strained n-channel metal-oxide-semiconductor field-effect transistors
 2014-05-19
2 The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors
 2012-11-26
3 Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC Applications
 2012-10-01
4 The investigation of charge loss mechanism in a two-bit wrapped-gate nitride storage nonvolatile memory
 2010-11-01
5 The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors
 2010-03-01
6 The Understanding of Strain-Induced Device Degradation in Advanced MOSFETs with Process-Induced Strain Technology of 65nm Node and Beyond
 2010-01-01
7 A New and Simple Experimental Approach to Characterizing the Carrier Transport and Reliability of Strained CMOS Devices in the Quasi-Ballistic Regime 2009-01-01
8 Design of High-Performance and Highly Reliable nMOSFETs with Embedded Si:C S/D Extension Stressor(Si:C S/D-E) 2009-01-01
9 A New Observation of Strain-Induced Slow Traps in Advanced CMOS Technology with Process-Induced Strain Using Random Telegraph Noise Measurement 2009-01-01
10 The investigation of capture/emission mechanism in high-k gate dielectric soft breakdown by gate current random telegraph noise approach
 2008-11-24
11 More Strain and Less Stress- The Guideline for Developing High-End Strained CMOS Technologies with Acceptable Reliability 2008-01-01
12 The Observation of Trapping and Detrapping Effects in High-k Gate Dielectric MOSFETs by a New Gate Current Random Telegraph Noise (I(G)-RTN) Approach 2008-01-01
13 New Observation of an Abnormal Leakage Current in Advanced CMOS Devices with Short Channel Lengths Down to 50nm and Beyond 2008-01-01
14 The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology
 2008-01-01
15 Technology roadmaps on the ballistic transport in strain engineered nanoscale CMOS devices 2007-01-01
16 Novel ultra-low voltage and high-speed programming/erasing schemes for SONOS flash memory with excellent data retention
 2007-01-01
17 The channel backscattering characteristics of sub-100nm CMOS devices with different channel/substrate orientations 2007-01-01
18 Impact of STI on the reliability of narrow-width pMOSFETs with advanced ALD N/O gate stack
 2006-03-01
19 Characterization of hot-hole injection induced SILC and related disturbs in flash memories
 2001-02-01
20 New degradation mechanisms of width-dependent hot carrier effect in quarter-micron shallow-trench-isolated p-channel metal-oxide-semiconductor field-effect-transistors
 2001-01-01
21 A new technique for hot carrier reliability evaluations of flash memory cell after long-term program/erase cycles
 1999-09-01
22 A new approach for characterizing structure-dependent hot-carrier effects in drain-engineered MOSFET's
 1999-07-01
23 A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage
 1998-11-01
24 A unified approach to profiling the lateral distributions of both oxide charge and interface states in n-MOSFET's under various bias stress conditions
 1997-11-01
25 An efficient method for characterizing time-evolutional interface state and its correlation with the device degradation in LDD n-MOSFET's
 1996-06-01
26 A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFET's
 1996-01-01

Patents

序號
No.		 標題
Title		 著作日期
Date
1 使用無源極和汲極接面場效電晶體之基本互補式邏輯閘之構造及其製造方法
 2014-01-11
2 使用無源極和汲極接面場效電晶體之基本互補式邏輯閘之構造及其製造方法
 2012-06-01

Plan

序號
No.		 標題
Title		 著作日期
Date
1 高性能先進三維閘極CMOS應變元件設計-元件至電路的考量 (II) 2014
2 高性能先進三維閘極CMOS應變元件設計---元件至電路的考量(I) 2013
3 先進奈米應力結構CMOS元件性能與可靠性變異之研究 2013
4 先進奈米應力結構CMOS元件性能與可靠性變異之研究 2012
5 下一世代高性能及高可靠性的N通道MOS元件設計及量測技術探討
 2011
6 先進奈米應力結構CMOS元件性能與可靠性變異之研究 2011
7 下一世代高性能及高可靠性的N通道MOS元件設計及量測技術探討
 2010
8 奈米CMOS元件不均勻、雜和氧化層缺陷導致臨限電壓變異之研究(I)
 2010
9 混合基片奈米CMOS元件技術中各種應力效應對傳輸特性及可靠性影響的研究
 2009
10 下一世代高性能及高可靠性的N通道MOS元件設計及量測技術探討
 2009
11 混合基片奈米CMOS元件技術中各種應力效應對傳輸特性及可靠性影響的研究 2008
12 高速操作及高資料保存特性SONOS型式快閃記憶體之研究 2008
13 高速操作及高資料保存特性SONOS型式快閃記憶體之研究 2007
14 混合基片奈米CMOS元件技術中各種應力效應對傳輸特性及可靠性影響的研究 2007
15 張力型矽鍺奈米CMOS元件通道工程及可靠性關鍵問題研究(III) 2007
16 高速操作及高資料保存特性SONOS型式快閃記憶體之研究 2006
17 張力型矽鍺奈米CMOS元件通道工程及可靠性關鍵問題研究(II) 2006
18 採用高層次操作模式及閘氧化層的高性能及可靠性SONOS快閃記憶體之研究(III) 2006
19 採用高層次操作模式及閘氧化層的高性能及可靠性SONOS快閃記憶體之研究(II) 2005
20 張力型矽鍺奈米CMOS元件通道工程及可靠性關鍵問題研究(I) 2005
21 高介電氧化層奈米CMOS元件可靠性關鍵問題及界面量測技術研究(II)
 2004
22 採用高層次操作模式及閘氧化層的高性能及可靠性SONOS快閃記憶體之研究(I)
 2004
23 高介電氧化層奈米CMOS元件可靠性關鍵問題及界面量測技術研究(I)
 2003
24 先進低電壓低功率及高效能快閃式記憶體之研究(III)
 2003
25 先進低電壓低功率及高效能快閃式記憶體之研究(II)
 2002
26 超薄氮化閘極氧化層奈米CMOS元件可靠性的新方法研究
 2002
27 高介電閘氧化層深次微米MOS元件電漿製程傷害可靠性之研究
 2001
28 先進低電壓低功率及高效能快閃式記憶體之研究(I)
 2001
29 不同型摻雜材料浮動閘極快閃式記憶元件可靠性問題之研究
 2000
30 利用電荷幫浦分佈法研究深次微米N型MOS元件電漿製程傷害之可靠性
 2000
31 用於快閃式記憶元件及電路性能與可靠性模擬的元件模式
 2000
32 利用氘化及氮化處理製備高可靠性薄閘氧化層深次微米NMOS元件
 2000
33 薄閘氧化層深次微米n-MOS元件的熱載子可靠性分析
 1999
34 P通道快閃式記憶元件在長時間寫入抹除後由熱載子導致的可靠性問題研究
 1999
35 快閃式記憶元件熱電子效應的可靠性分析 1996
36 具有反向短通道效應N型MOS元件性能及可靠性的研究 1996
37 次微米MOS元件中反向短通道效應特性分析與模式 1995
38 EPROM記憶元件中熱電子效應的可靠性研究 1995
39 次微米MOS元件在非熱平衡下含氧化層傷害之熱電子閘極電流模式 1994

Proceedings Paper

序號
No.		 標題
Title		 著作日期
Date
1 The Physical Insights Into an Abnormal Erratic Behavior in the Resistance Random Access Memory 2013-01-01
2 The Understanding of the Bulk Trigate MOSFET's Reliability Through the Manipulation of RTN Traps 2013-01-01
3 The Variability Issues in Small Scale Trigate CMOS Devices: Random Dopant and Trap Induced Fluctuations 2013-01-01
4 The Understanding of Multi-level RTN in Trigate MOSFETs Through the 2D Profiling of Traps and Its Impact on SRAM Performance: A New Failure Mechanism Found 2012-01-01
5 Experimental Observation on the Random Dopant Fluctuation of Small Scale Trigate CMOS Devices 2012-01-01
6 New Observations on the Physical Mechanism of Vth-Variation in Nanoscale CMOS Devices After Long Term Stress 2011-01-01
7 Extension of Moore's Law Via Strained Technologies-The Strategies and Challenges
 2011-01-01
8 Low Voltage and High Speed SONOS Flash Memory Technology: The Strategies and the Reliabilities
 2010-01-01
9 The State-of-the-Art Mobility Enhancing Schemes for High-Performance Logic CMOS Technologies
 2008-01-01
10 The incremental frequency charge pumping method: Extending the CMOS ultra-thin gate oxide measurement down to 1nm
 2007-01-01
11 New observations on the uniaxial and biaxial strain-induced hot carrier and NBTI Reliabilities for 65nm node CMOS devices and beyond 2006-01-01
12 Understanding of the leakage components and its correlation to the oxide scaling on the SONOS cell endurance and retention 2006-01-01
13 Twin-GD: A new twin gated-diode measurement for the interface characterization of ultra-thin gate oxide MOSFET's with EOT down to 1nm 2006-01-01
14 Reliability issues for high performance nanoscale CMOS technologies with channel mobility enhancing schemes
 2006-01-01
15 A new insight into the degradation mechanisms of various mobility-enhanced CMOS devices with different substrate engineering 2005-01-01
16 A new observation of the germanium outdiffusion effect on the hot carrier and NBTI reliabilities in sub-100nm technology strained-Si/SiGe CMOS devices 2005-01-01
17 Different approaches for reliability enhancement of p-channel flash memory
 2004-01-01
18 An accurate RF CMOS gate resistance model compatible with HSPICE 2004-01-01
19 Low leakage reliability characterization methodology for advanced CMOS with gate oxide in the 1nm range
 2004-01-01
20 The impact of STI induced reliabilities for scaled p-MOSFET in an advanced multiple oxide CMOS technology 2004-01-01
21 The performance and reliability enhancement of ETOX P-channel flash EEPROM cell with P-doped floating-gate
 2003-01-01
22 A novel leakage current separation technique in a direct Tunneling regime gate oxide SONOS memory cell 2003-01-01
23 An improved interface characterization technique for a full-range profiling of oxide damage in ultra-thin gate oxide CMOS devices 2003-01-01
24 Localization of NBTI-induced oxide damage in direct tunneling regime gate oxide pMOSFET using a novel low gate-leakage gated-diode (L-2-GD) method 2002-01-01
25 A novel and direct determination of the interface traps in sub-100nm CMOS devices with direct tunneling regime (12 similar to 16A) gate oxide
 2002-01-01
26 New experimental evidences of the plasma charging enhanced hot carrier effect and its impact on surface channel CMOS devices
 2001-01-01
27 A new physical and quantitative width dependent hot carrier model for shallow-trench-isolated CMOS devices 2001-01-01
28 N-channel versus P-channel flash EEPROM - Which one has better reliabilities 2001-01-01
29 Universal switched-current integrator blocks for SI filter design
 1999-01-01
30 An accurate hot carrier reliability monitor for deep-submicron shallow S/D junction thin gate oxide n-MOSFET's
 1999-01-01
31 New insight into the degradation mechanism of nitride spacer with different post-oxide in submicron LDD n-MOSFET's
 1998-03-01
32 Performance and reliability evaluations of P-channel flash memories with different programming schemes
 1997-01-01
33 A new bride damage characterization technique for evaluating hot carrier reliability of flash memory cell after P/E cycles 1997-01-01
34 A physically-based built-in Spice Poly-Si TFT model for circuit simulation and reliability evaluation
 1996-01-01
35 A numerical model for simulating MOSFET gate current degradation by considering the interface state generation 1996-01-01
36 A NEW PROFILING TECHNIQUE FOR CHARACTERIZING HOT-CARRIER-INDUCED OXIDE DAMAGES IN LDD-N-MOSFETS
 1995-06-01
37 Accurate MOS device hot carrier models for VLSI reliability simulation
 1995-01-01
38 Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement results
 1995-01-01

Thesis

序號
No.		 標題
Title		 著作日期
Date
1 三維金氧半電晶體基本邏輯閘電路的變異性模型 2014
2 雙介電層低功耗電阻式記憶體之設計與導通機制探討 2014
3 探討金屬高介電層互補式金氧半電晶體崩潰的新穎方法 2014
4 U型多重讀寫氮化矽快閃式記憶體之耐久性及資料保存探討 2013
5 閘極漏電流的變異對三維金氧半電晶體的影響 2013
6 The Study of Device Characteristics and the Random Telegraph Noise Analysis in HfO2-based Resistive Random Access Memory 2013
7 由實驗方法分析三維金氧半電晶體的彈道傳輸特性 2013
8 二氧化鉿高介電層之N通道金氧半電晶體氧化層缺陷研究 2013
9 使用新的量測方法探討三面閘極金氧半電晶體 氧化層隨機陷阱造成之擾動效應
 2012
10 運用隨機電報訊號方法分析三閘極電晶體的多層級氧化層陷阱 2012
11 二氧化鉿電阻式記憶體多位元操作之隨機電報雜訊分析 2012
12 CMOS製程相容U型多重讀寫氮化矽快閃式記憶體之物理機制與可靠性探討 2012
13 應變矽CMOS元件中隨機摻雜與隨機界面缺陷引起的臨界電壓變異度研究
 2010
14 決定高效能蕭特基金氧半場效應電晶體傳輸參數的新實驗方法
 2010
15 二位元分離式閘極氮化矽快閃式記憶體之先進操作方法探討
 2010
16 隨機電報訊號量測法應用於前瞻CMOS元件應變技術引致的汲極電流不穩定性之研究
 2009
17 奈米級蕭特基金氧半場效電晶體之載子傳輸特性與通道背向散射研究
 2009
18 隨機電報訊號量測於高閘極介電層N通道金氧半電晶體汲極電流波動之探討 2009
19 二氧化鉿薄膜電阻式隨機存取記憶體之轉換機制及可靠度探討
 2009
20 二氧化鉿基底電阻式記憶體之動態轉換物理模型
 2009
21 二位元分離式閘極氮化矽快閃式記憶體之漏電機制探討
 2009
22 奈米應變矽元件載子傳輸模型分析與其可靠度相關性探討 2008
23 一種改良的介面缺陷之橫向剖面分析應用於奈米級應變矽CMOS元件之可靠度探討
 2007
24 二位元SONOS快閃式記憶體之物理機制與可靠性探討
 2007
25 探討高閘極介電層N通道金氧半電晶體的新穎閘極電流隨機電報量測法
 2007
26 以鉿為基底之高介電常數閘極介電層之N通道金氧半電晶體可靠度探討
 2007
27 低電壓且高速操作的P通道快閃式記憶體元件性能及可靠性研究
 2006
28 奈米應變矽CMOS元件之通道背向散射特性與可靠度之相關性研究
 2006
29 氮化矽記憶體元件資料保存及耐久性之探討
 2004
30 不同界面層與環狀植入對高介電氧化層CMOS元件可靠性影響之研究 2004
31 應變矽奈米CMOS元件的熱載子可靠性研究與分析
 2004
32 高介電氧化層MOSFET元件之低漏電電荷幫浦量測技術
 2004
33 先進互補式金氧半元件的閘極層厚度1nm範圍下之低漏電電荷幫浦量測技術
 2003
34 先進氮化超薄氧化層及堆疊氧化層結構CMOS元件在熱載子與高溫負偏壓操作下的探討 2003
35 具有直接穿隧氧化層氮化矽記憶體資料保存特性之探討 2002
36 利用閘二極體量測法評估雙閘極金氧半電晶體的熱載子和負偏壓溫度可靠性 2001
37 利用汲極端包覆性植入結構改善快閃記憶體的性能與可靠性之研究 2001
38 高頻CMOS元件基板SPICE模型建立 2001
39 深次微米與奈米金氧半元件氧化層界面與製程導致元件可靠性的探討 2001
40 不同浮動閘極材料P通道快閃記憶體性能與可靠性之改進 2000
41 用於射頻積體電路模擬的閘極電阻準確模型 2000
42 利用汲極崩潰熱電子注入操作的快閃式記憶體元件性能及可靠性研究 2000
43 使用多重氧化層技術成長之雙閘極金氧半元件偏壓與溫度效應之可靠性研究 2000
44 不同浮動閘極材料N通道快閃記憶體資料保存特性研究 1999
45 電荷幫浦法於薄閘極氧化層淺接面延伸結構之N型金氧半元件電漿蝕刻傷害之研究 1999
46 應用於電路模擬器含有溫度效應的複晶矽薄膜電晶體模式 1999
47 一種用於低功率及高效率快閃式記憶體之新型寫入方式 1999
48 以基極偏壓增強熱電子注入操作的快閃式記憶元件可靠性研究 1999
49 快閃式記憶元件中熱載子注入導致的可靠性問題研究 1998
50 N與P通道快閃記憶體性能與可靠性之比較研究 1998
51 利用P型浮動閘極材料改善N通道快閃記憶體的性能與可靠性之研究 1998
52 可用於快閃式記憶體反覆寫入抹除前後之直流與暫態模式 1998
53 淺凹槽隔離深次微米互補金氧半元件窄寬度效應熱載子可靠性的研究 1998
54 單調迭代法半導體元件方程式數值解 1997
55 P通道金屬半快閃式記憶體中不同程式化的可靠性評估 1996
56 高介電係數夾層LDD N型金氧半元件可靠性設計之探討 1996
57 次微米N型MOS元件中反向短通道效應之模式及其特性分析 1996
58 半空乏型矽氧化絕緣基片MOS元件之熱電子可靠性 1995
59 供電路模擬器SPICE使用之複晶矽薄膜電晶體模式 1995
60 次微米MOS元件中熱電子導致氧化層傷害及元件特性退化分析 1995
61 次微米LDD結構金氧半元件之熱載子可靠性分析與模式研究 1994
62 次微米MOS SOI元件之分析與設計 1994
63 不同閘極結構高壓複晶矽薄膜電晶體的二維模擬與分析 1994
64 不同氧化層厚度次微米 LDD MOS 元件中熱載子導致元件的退化分析 1994
65 交換電流式積分器之設計及其在濾波器設計上之應用 1994
66 VLSI可靠性中由熱載子產生氧化層傷害的模式與模擬 1993
67 小型化金氧半場效電晶體之新的參數擷取法與模式之建立 1993
68 次微米MOS元件中因熱載子效應引起氧化層傷害之探討 1992
69 次微米大斜角植入式金氧半元件之特性分析與設計準則 1992
70 超大型積體電路類比數位混合式模擬器之設計 1992
71 次微米金氧半元件熱電子效應的二維流體動力模擬與模式 1991
72 短通道金氧半電晶體的本質電容解析模式 1991
73 LOCOS閘極結構次微米金氧半元件的模式研究 1991
74 渠溝隔離金氧半電晶體的糢擬與模式 1989
75 電路模擬用金氧半電晶體熱電子效應模式 1989
76 三維雜散電容模擬器及其在唯讀記憶體設計上的應用 1989
77 交流工作下金氧半電晶體熱電子效應的暫態模擬與模式 1989
78 次微米 LDD金氧半電晶體製程及元件的設計 1989
79 利用波形鬆弛法於超大型積體電氌的平行模擬 1989
80 交流工作下金氧半電晶體熱電子效應的暫態模擬與模式 1989
81 LDD 金氧半電晶體本質電容模式 1987
82 具有佈植通道的短通道MOSFET電流-電壓模式 1987
83 次微米大斜角植入式金氧半元件之特性分析與設計準則 1984
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