1. 目前位置：
柯明道

柯明道 Ker, Ming-Dou

電子郵件／E-mail：mdker@ieee.org

服務單位／Department：電機學院 ／ 電子工程學系及電子研究所

著作期間／Publish Period：1970-01-01 - 2014-10-01

著作統計／Statistics

Article（171）
Others（5）
Patents（62）
Plan（31）
Proceedings Paper（140）
Thesis（87）

Article

序號
No.		 標題
Title		 著作日期
Date
1 On-Chip Transient Voltage Suppressor Integrated With Silicon-Based Transceiver IC for System-Level ESD Protection
 2014-10-01
2 Investigating electron depletion effect in amorphous indium-gallium-zinc-oxide thin-film transistor with a floating capping metal by technology computer-aided design simulation and leakage reduction
 2014-06-01
3 Local CDM ESD Protection Circuits for Cross-Power Domains in 3D IC Applications
 2014-06-01
4 Evaluation of subcortical grey matter abnormalities in patients with MRI-negative cortical epilepsy determined through structural and tensor magnetic resonance imaging
 2014-05-14
5 Design of high-voltage-tolerant stimulus driver with adaptive loading consideration to suppress epileptic seizure in a 0.18-mu m CMOS process
 2014-05-01
6 Layout Consideration and Circuit Solution to Prevent EOS Failure Induced by Latchup Test in a High-Voltage Integrated Circuits
 2014-03-01
7 On the Design of Power-Rail ESD Clamp Circuits With Gate Leakage Consideration in Nanoscale CMOS Technology
 2014-03-01
8 Synthesis of uniform core-shell gelatin-alginate microparticles as intestine-released oral delivery drug carrier
 2014-02-01
9 A Fully Integrated 8-Channel Closed-Loop Neural-Prosthetic CMOS SoC for Real-Time Epileptic Seizure Control
 2014-01-01
10 Metal-layer capacitors in the 65 nm CMOS process and the application for low-leakage power-rail ESD clamp circuit
 2014-01-01
11 SCR-based transient detection circuit for on-chip protection design against system-level electrical transient disturbance
 2014-01-01
12 Through Diffusion Tensor Magnetic Resonance Imaging to Evaluate the Original Properties of Neural Pathways of Patients with Partial Seizures and Secondary Generalization by Individual Anatomic Reference Atlas
 2014-01-01
13 Robust ESD Protection Design for 40-Gb/s Transceiver in 65-nm CMOS Process
 2013-11-01
14 Design of 2 x V-DD-Tolerant I/O Buffer With PVT Compensation Realized by Only 1 x V-DD Thin-Oxide Devices
 2013-10-01
15 Power-Rail ESD Clamp Circuit With Diode-String ESD Detection to Overcome the Gate Leakage Current in a 40-nm CMOS Process
 2013-10-01
16 A Latchup-Immune and Robust SCR Device for ESD Protection in 0.25-mu m 5-V CMOS Process
 2013-05-01
17 Implantable Stimulator for Epileptic Seizure Suppression With Loading Impedance Adaptability
 2013-04-01
18 Design of Dual-Band ESD Protection for 24-/60-GHz Millimeter-Wave Circuits
 2013-03-01
19 High Area-Efficient ESD Clamp Circuit With Equivalent RC-Based Detection Mechanism in a 65-nm CMOS Process
 2013-03-01
20 Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
 2013-02-01
21 PMOS-based power-rail ESD clamp circuit with adjustable holding voltage controlled by ESD detection circuit
 2013-02-01
22 Resistor-Less Design of Power-Rail ESD Clamp Circuit in Nanoscale CMOS Technology
 2012-12-01
23 Investigation on CDM ESD events at core circuits in a 65-nm CMOS process
 2012-11-01
24 Power-Rail ESD Clamp Circuit With Ultralow Standby Leakage Current and High Area Efficiency in Nanometer CMOS Technology
 2012-10-01
25 Design of Compact ESD Protection Circuit for V-Band RF Applications in a 65-nm CMOS Technology
 2012-09-01
26 Study of intrinsic characteristics of ESD protection diodes for high-speed I/O applications
 2012-06-01
27 Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits
 2012-06-01
28 Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection
 2012-03-01
29 New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology
 2012-03-01
30 ESD Protection Design for 60-GHz LNA With Inductor-Triggered SCR in 65-nm CMOS Process
 2012-03-01
31 New 4-Bit Transient-to-Digital Converter for System-Level ESD Protection in Display Panels
 2012-02-01
32 Design of Integrated Gate Driver With Threshold Voltage Drop Cancellation in Amorphous Silicon Technology for TFT-LCD Application
 2011-12-01
33 Stimulus driver for epilepsy seizure suppression with adaptive loading impedance
 2011-12-01
34 New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process
 2011-09-01
35 Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process
 2011-09-01
36 Design and implementation of configurable ESD protection cell for 60-GHz RF circuits in a 65-nm CMOS process
 2011-08-01
37 Digital time-modulation pixel memory circuit in LTPS technology 2011-08-01
38 Design and implementation of readout circuit on glass substrate with digital correction for touch-panel applications 2011-07-01
39 Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
 2011-06-01
40 Design to suppress return-back leakage current of charge pump circuit in low-voltage CMOS process
 2011-05-01
41 Design and Implementation of Readout Circuit with Threshold Voltage Compensation on Glass Substrate for Touch Panel Applications
 2011-03-01
42 Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
 2011-02-01
43 Design of Analog Pixel Memory for Low Power Application in TFT-LCDs
 2011-02-01
44 ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology
 2010-12-01
45 Implementation of delta-sigma analog-to-digital converter in LTPS process 2010-11-01
46 Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection
 2010-11-01
47 New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance
 2010-10-01
48 Design and Implementation of Readout Circuit on Glass Substrate for Touch Panel Applications
 2010-08-01
49 High-Voltage-Tolerant ESD Clamp Circuit With Low Standby Leakage in Nanoscale CMOS Process
 2010-07-01
50 Design of 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Consideration of Gate Leakage Current in 65-nm CMOS Technology
 2010-06-01
51 Design of differential low-noise amplifier with cross-coupled-SCR ESD protection scheme
 2010-06-01
52 Investigation on NMOS-based power-rail ESD clamp circuits with gate-driven mechanism in a 0.13-mu m CMOS technology
 2010-06-01
53 Optimization on Layout Style of ESD Protection Diode for Radio-Frequency Front-End and High-Speed I/O Interface Circuits
 2010-06-01
54 Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
 2010-05-01
55 New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS
 2010-02-01
56 Design of 2xVDD-tolerant mixed-voltage I/O buffer against gate-oxide reliability and hot-carrier degradation
 2010-01-01
57 2xVDD-Tolerant Power-Rail ESD Clamp Circuit With Low Standby Leakage in 65-nm CMOS Process 2010-01-01
58 ESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchup 2010-01-01
59 Self-Matched ESD Cell in CMOS Technology for 60-GHz Broadband RF Applications
 2010-01-01
60 A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY
 2010-01-01
61 New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process
 2009-12-01
62 Digital-to-analog converter with gamma correction on glass substrate for TFT-panel applications 2009-10-01
63 Design of Analog Output Buffer With Level Shifting Function on Glass Substrate for Panel Application
 2009-09-01
64 Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology
 2009-08-01
65 Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs
 2009-08-01
66 Optimization on MOS-Triggered SCR Structures for On-Chip ESD Protection
 2009-07-01
67 Low-capacitance ESD protection design for high-speed I/O interfaces in a 130-nm CMOS process
 2009-06-01
68 Transient-Induced Latchup in CMOS ICs Under Electrical Fast-Transient Test
 2009-06-01
69 The Effect of IEC-Like Fast Transients on RC-Triggered ESD Power Clamps
 2009-06-01
70 A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process
 2009-05-01
71 Area-Efficient ESD-Transient Detection Circuit With Smaller Capacitance for On-Chip Power-Rail ESD Protection in CMOS ICs
 2009-05-01
72 High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection
 2009-04-01
73 Impedance-Isolation Technique for ESD Protection Design in RF Integrated Circuits
 2009-03-01
74 Design of High-Voltage-Tolerant ESD Protection Circuit in Low-Voltage CMOS Processes
 2009-03-01
75 Board-Level ESD of Driver ICs on LCD Panel
 2009-03-01
76 Design of Power-Rail ESD Clamp Circuit With Ultra-Low Standby Leakage Current in Nanoscale CMOS Technology
 2009-03-01
77 Investigation on Board-Level CDM ESD Issue in IC Products
 2008-12-01
78 Investigation on Robustness of CMOS Devices Against Cable Discharge Event (CDE) Under Different Layout Parameters in a Deep-Submicrometer CMOS Technology
 2008-11-01
79 Temperature Coefficient of Poly-Silicon TFT and Its Application on Voltage Reference Circuit With Temperature Compensation in LTPS Process
 2008-10-01
80 Low-capacitance and fast turn-on SCR for RF ESD protection
 2008-08-01
81 Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP)
 2008-07-01
82 Impact of MOSFET gate-oxide reliability on CMOS operational amplifier in a 130-nm low-voltage process
 2008-06-01
83 ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers
 2008-06-01
84 Circuit performance degradation of switched-capacitor circuit with bootstrapped technique due to gate-oxide overstress in a 130-nm CMOS process
 2008-03-01
85 On-chip transient detection circuit for system-level ESD protection in CMOS integrated circuits to meet electromagnetic compatibility regulation
 2008-02-01
86 ESD protection design for fully integrated CMOS RF power amplifiers with waffle-structured SCR 2008-01-01
87 2xVDD-tolerant crystal oscillator circuit realized with 1xVDD CMOS devices without gate-oxide reliability issue 2008-01-01
88 Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration 2008-01-01
89 The impact of gate-oxide breakdown on common-source-amplifiers with diode-connected active load in low-voltage CMOS processes
 2007-11-01
90 On-chip ESD protection design for automotive vacuum-fluorescent-display (VFD) driver IC to sustain high ESD stress
 2007-09-01
91 New gate-bias voltage-generating technique with threshold-voltage compensation for on-glass analog circuits in LTPS process
 2007-09-01
92 Transient-induced latchup dependence on power-pin damping frequency and damping factor in CMOS integrated circuits
 2007-08-01
93 Fabrication of a miniature CMOS-based optical biosensor
 2007-06-15
94 Implementation of initial-on ESD protection concept with PMOS-triggered SCR devices in deep-submicron CMOS technology
 2007-05-01
95 Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs
 2007-04-01
96 Test structure on SCR device in waffle layout for RE ESD protection
 2007-01-01
97 Design of mixed-voltage crystal oscillator circuit in low-voltage CMOS technology
 2007-01-01
98 ESD protection design for giga-Hz high-speed I/O interfaces in a 130-nm CMOS process 2007-01-01
99 An output buffer for 3.3-V applications in a 0.13-mu m 1/2.5-V CMOS process
 2007-01-01
100 Ultra-high-voltage charge pump circuit in low-voltage bulk CMOS processes with polysilicon diodes
 2007-01-01
101 Overview on ESD protection design for mixed-voltage I/O interfaces with high-voltage-tolerant power-rail ESD clamp circuits in low-voltage thin-oxide CMOS technology
 2007-01-01
102 Bond pad design with low capacitance in CMOS technology for RF applications
 2007-01-01
103 ESD-protection design with extra low-leakage-current diode string for RF circuits in SiGeBiCMOS process
 2006-12-01
104 ESD robustness of thin-film devices with different layout structures in LTPS technology
 2006-12-01
105 Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
 2006-10-01
106 Design of mixed-voltage I/O buffer by using NMOS-blocking technique
 2006-10-01
107 Component-level measurement for transient-induced latch-up in CMOS ICs under system-level ESD considerations
 2006-09-01
108 Overview and design of mixed-voltage I/O buffers, with low-voltage thin-oxide CMOS transistors
 2006-09-01
109 New curvature-compensation technique for CMOS bandgap reference with sub-1-V operation
 2006-08-01
110 Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology
 2006-07-01
111 On-Panel Output Buffer With Offset Compensation Technique for Data Driver in LTPS Technology
 2006-06-01
112 Design of charge pump circuit with consideration of gate-oxide reliability in low-voltage CMOS processes
 2006-05-01
113 ESD failure mechanisms of analog I/O cells in 0.18-mu m CMOS technology
 2006-03-01
114 Overview on electrostatic discharge protection designs for mixed-voltage I/O interfaces: Design concept and circuit implementations
 2006-02-01
115 Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
 2006-02-01
116 Electrostatic discharge protection scheme without leakage current path for CMOS IC operating in power-down-mode condition on a system board
 2006-02-01
117 ESD protection design for I/O cells with embedded SCR structure as power-rail ESD clamp device in nanoscale CMOS technology
 2005-11-01
118 ESD protection design of low-voltage-triggered p-n-p devices and their failure modes in mixed-voltage I/O interfaces with signal levels higher than VDD and lower than VSS
 2005-09-01
119 Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test
 2005-08-01
120 The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
 2005-08-01
121 A new Schmitt trigger circuit in a 0.13-mu m 1/2.5-V CMOS process to receive 3.3-V input signals
 2005-07-01
122 Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
 2005-06-01
123 SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology
 2005-05-01
124 ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
 2005-05-01
125 MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process 2005-03-01
126 ESD protection design for mixed-voltage I/O buffer with substrate-triggered circuit
 2005-01-01
127 SCR device with dynamic holding voltage for on-chip ESD protection in a 0.25-mu m fully salicided CMOS process
 2004-10-01
128 On-chip ESD protection design with substrate-triggered technique for mixed-voltage I/O circuits in subquarter-micrometer CMOS process
 2004-10-01
129 ESD protection design to overcome internal damage on interface circuits,of a CMOS IC with multiple separated power pins
 2004-09-01
130 Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
 2004-09-01
131 Investigation on device characteristics of MOSFET transistor placed under bond pad for high-pin-count SOC applications
 2004-09-01
132 Design on ESD protection scheme for IC with power-down-mode operation
 2004-08-01
133 Design optimization of ESD protection and latchup prevention for a serial I/O IC
 2004-02-01
134 Active electrostatic discharge (ESD) device for on-chip ESD protection in sub-quarter-micron complementary metal-oxide semiconductor (CMOS) process
 2004-01-15
135 Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection
 2003-11-15
136 ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness
 2003-10-01
137 SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
 2003-09-01
138 Latchup-free ESD protection design with complementary substrate-triggered SCR devices
 2003-08-01
139 Analysis on the dependence of layout parameters on ESD robustness of CMOS devices for manufacturing in deep-submicron CMOS process
 2003-08-01
140 Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product
 2003-08-01
141 High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-micron complementary metal oxide semiconductor technology
 2003-06-01
142 CMOS chip as luminescent sensor for biochemical reactions
 2003-06-01
143 Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology
 2003-05-01
144 Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
 2003-04-01
145 Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
 2003-02-01
146 Substrate-triggered ESD protection circuit without extra process modification
 2003-02-01
147 Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
 2002-11-15
148 Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
 2002-08-01
149 ESD protection design for CMOS RF integrated circuits using polysilicon diodes
 2002-06-01
150 Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs
 2002-06-01
151 Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
 2002-06-01
152 Substrate-triggered ESD clamp devices for use in power-rail ESD clamp circuits
 2002-05-01
153 Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
 2001-12-01
154 On-chip ESD protection design by using polysilicon diodes in CMOS process
 2001-04-01
155 Hardware/firmware co-design in an 8-bits microcontroller to solve the system-level ESD issue on keyboard
 2001-03-01
156 ESD protection design on analog pin with very low input capacitance for high-frequency or current-mode applications
 2000-08-01
157 Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
 2000-04-01
158 Cascoded LVTSCR with tunable holding voltage for ESD protection in bulk CMOS technology without latchup danger
 2000-03-01
159 New layout design for submicron CMOS output transistors to improve driving capability and ESD robustness
 1999-03-01
160 Design of dynamic-floating-gate technique for output ESD protection in deep-submicron CMOS technology
 1999-02-01
161 Improved output ESD protection by dynamic gate floating design
 1998-09-01
162 Multiple-cell square-type layout design for output transistors in submicron CMOS technology to save silicon area
 1998-06-01
163 A gate-coupled PTLSCR/NTLSCR ESD protection circuit for deep-submicron low-voltage CMOS IC's
 1997-01-01
164 Capacitor-couple ESD protection circuit for deep-submicron low-voltage CMOS ASIC
 1996-09-01
165 Complementary-LVTSCR ESD protection circuit for submicron CMOS VLSI/ULSI
 1996-04-01
166 COMPLEMENTARY-SCR ESD PROTECTION CIRCUIT WITH INTERDIGITATED FINGER-TYPE LAYOUT FOR INPUT PADS OF SUBMICRON CMOS ICS
 1995-07-01
167 MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION
 1995-06-01
168 MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .2. QUANTITATIVE-EVALUATION
 1995-06-01
169 TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION 1994-02-01
170 CMOS ON-CHIP ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT USING 4-SCR STRUCTURES WITH LOW ESD-TRIGGER VOLTAGE 1994-01-01
171 A NEW ON-CHIP ESD PROTECTION CIRCUIT WITH DUAL PARASITIC SCR STRUCTURES FOR CMOS VLSI
 1992-03-01

Others

序號
No.		 標題
Title		 著作日期
Date
1 Foreword for the Special Issue on ESD Technology
 2012-12-01
2 CLOSE-LOOP EPILEPSY PROSTHESIS DEVICES WITH SPATIAL-TEMPORAL SEIZURE DETECTION AND RESPONSIVELY THERAPEUTIC STIMULATION 2011-08-01
3 NCTU Biomimetic Syst Res Ctr 1970-01-01
4 NCTU Biomimetic Syst Res Ctr 1970-01-01
5 NCTU Biomimetic Syst Res Ctr 1970-01-01

Patents

序號
No.		 標題
Title		 著作日期
Date
1 具負載適應性之生物電流刺激器
 2014-08-01
2 自動重置之暫態數位轉換器及電子產品
 2014-03-21
3 具有多指矽控整流器之靜電保護電路
 2014-03-01
4 靜電放電防護裝置
 2013-11-21
5 靜電放電防護裝置及靜電放電防護電路
 2013-08-21
6 靜電放電保護裝置
 2013-08-21
7 自動重置之暫態數位轉換器及電子產品
 2013-07-01
8 電流刺激裝置
 2013-07-01
9 静电放电防护装置及静电放电防护电路 2013-03-27
10 暫態偵測電路
 2012-12-11
11 具負載適應性之生物電流刺激器
 2012-11-16
12 雜訊過濾電路以及積體電路
 2012-10-16
13 暫態偵測電路以及積體電路
 2012-08-01
14 靜電放電防護裝置
 2012-06-16
15 静电放电防护装置及静电放电防护电路 2011-12-07
16 靜電放電防護裝置及靜電放電防護電路
 2011-12-01
17 靜電放電防護裝置以及積體電路
 2011-10-21
18 靜電放電保護裝置
 2011-08-01
19 數位轉換器及具有數位轉換器之電子裝置
 2010-12-21
20 採用低電壓元件之混合電壓石英振盪電路
 2010-11-21
21 混合電壓輸入／輸出緩衝器
 2010-08-01
22 ELECTROSTATIC DISCHARGE PROTECTION DEVICE AND RELATED CIRCUIT
 2010-06-10
23 ESD PROTECTION CIRCUITRY WITH MULTI-FINGER SCRS
 2010-05-13
24 暫態偵測電路
 2009-11-01
25 TRANSIENT DETECTION CIRCUIT
 2009-10-29
26 TRANSIENT TO DIGITAL CONVERTERS
 2009-09-17
27 數位轉換器及具有數位轉換器之電子產品
 2009-09-16
28 暫態偵測電路以及積體電路
 2009-08-01
29 TRANSIENT DETECTION CIRCUIT FOR ESD PROTECTION
 2009-07-23
30 SILICON CONTROLLED RECTIFIER
 2009-07-16
31 POWER-RAIL ESD PROTECTION CIRCUIT WITHOUT LOCK-ON FAILURE
 2009-04-02
32 靜電放電防護裝置以及積體電路
 2009-04-01
33 採用低電壓元件之混合電壓石英振盪電路
 2008-12-16
34 具有低電壓元件設計之混合電壓輸入／輸出緩衝器
 2008-10-11
35 MIXED-VOLTAGE INPUT/OUTPUT BUFFER
 2008-07-03
36 混合電壓輸入／輸出緩衝器
 2008-07-01
37 具三倍電壓耐受能力之電源線間靜電放電防護電路
 2008-05-21
38 具有低電壓元件設計之混合電壓輸入／輸出緩衝器
 2007-12-01
39 Mixed voltage input/output buffer having low-voltage design
 2007-11-29
40 具三倍電壓耐受能力之電源線間靜電放電防護電路
 2007-10-16
41 HIGH-VOLTAGE TOLERANT POWER-RAIL ESD CLAMP CIRCUIT
 2007-10-04
42 利用NMOS來保護混合電壓輸入輸出介面之電路
 2007-02-11
43 利用NMOS來保護混合電壓輸入輸出介面之電路
 2007-01-16
44 可避免鎖住效應之高壓積體電路電源間靜電放電箝制電路
 2006-09-11
45 具低壓差動訊號（LVDS）與低擺幅差動訊號（RSDS）規格之平面顯示器高速輸入輸出緩衝器
 2006-08-01
46 具低壓差動訊號（LVDS）與低擺幅差動訊號（RSDS）規格之平面顯示器高速輸入輸出緩衝器
 2006-07-16
47 可避免鎖住效應之高壓積體電路電源間靜電放電箝制電路
 2006-04-01
48 遞減面積之分散式靜電放電防護電路
 2006-02-16
49 遞減面積之分散式靜電放電防護電路
 2006-01-11
50 用以靜電放電防護之矽控整流器
 2005-12-16
51 Silicon controlled rectifier for the electrostatic discharge protection
 2005-12-08
52 靜電放電防護電路
 2005-10-16
53 靜電放電防護電路
 2005-08-16
54 適用於低電壓製程之電荷幫浦電路
 2005-07-16
55 Charge pump circuit suitable for low-voltage process
 2005-07-07
56 雙觸發矽控整流元件與使用其之靜電保護電路
 2005-07-01
57 [DOUBLE-TRIGGERED SILICON CONTROLLING RECTIFIER AND ELECTROSTATIC DISCHARGE PROTECTION CIRCUIT THEREOF]
 2005-06-23
58 適用於低電壓製程之電荷幫浦電路
 2005-06-01
59 靜電放電防護電路
 2005-05-01
60 用以靜電放電防護之矽控整流器
 2005-04-11
61 靜電放電防護電路
 2004-11-21
62 雙觸發矽控整流元件與使用其之靜電保護電路
 2004-11-01

Plan

序號
No.		 標題
Title		 著作日期
Date
1 前瞻性混合信號式電路設計技術開發---總計畫暨子計畫五：前瞻性靜電放電防護技術開發 2014
2 積體電路與電子系統之靜電放電防護技術產學聯盟( I ) 2014
3 腦功能手術之整合性顱內腦圖譜儀開發與驗證---子計畫五：應用於癲癇術中整合性顱內腦圖譜儀之雙相電流刺激器積體電路設計( I ) 2014
4 癲癇治療電子系統之研發及其動物實驗之驗證---子計畫七：應用於癲癇治療系統之雙極性電流刺激器電路設計( III ) 2013
5 前瞻性混合信號式電路設計技術開發-總計畫暨子計畫四：前瞻性靜電放電防護技術開發(I) 2012
6 癲癇治療電子系統之研發及其動物實驗之驗證-子計畫七：應用於癲癇治療系統之雙極性電流刺激器電路設計(2/3) 2012
7 先進之混合信號式電路設計技術開發-子計畫五：先進之靜電放電防護技術開發(I)
 2011
8 癲癇治療電子系統之研發及其動物實驗之驗證-子計畫七：應用於癲癇治療系統之雙極性電流刺激器電路設計( I ) 2011
9 先進之混合信號式電路設計技術開發-總計畫(I)
 2011
10 奈米級混合信號式電路技術---子計畫四：奈米級CMOS製程之積體電路靜電放電防護技術
 2010
11 奈米級混合信號式電路技術---總計畫 2010
12 智慧型仿生系統之晶片系統平台技術開發---子計畫三：應用於智慧型仿生系統晶片之高壓輸入/輸出電路設計(III) 2010
13 奈米級混合信號式電路技術---總計畫 2009
14 智慧型仿生系統之晶片系統平台技術開發---子計畫三：應用於智慧型仿生系統晶片之高壓輸入/輸出電路設計(II) 2009
15 奈米級混合信號式電路技術---子計畫四：奈米級CMOS製程之積體電路靜電放電防護技術
 2009
16 智慧型仿生系統之晶片系統平台技術開發---子計畫三：應用於智慧型仿生系統晶片之高壓輸入/輸出電路設計(I) 2008
17 奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---總計畫 2008
18 奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫二：極低寄生電容之靜電放電防護技術以應用於超高速/超高頻積體電路 2008
19 奈米CMOS之前瞻射頻類比電路設計---子計畫二：奈米CMOS射頻類比電路之可靠度設計與研究(III) 2007
20 奈米CMOS之前瞻射頻類比電路設計---總計畫(III) 2007
21 奈米CMOS之前瞻射頻類比電路設計---子計畫二：奈米CMOS射頻類比電路之可靠度設計與研究(II) 2006
22 奈米CMOS之前瞻射頻類比電路設計---總計畫(II) 2006
23 用於儲存與區域網路之160Gbps乙太網路光電技術開發---子計畫五：160Gbps乙太網路收發介面電路之靜電放電防護設計(I) 2006
24 用於儲存與區域網路之160Gbps乙太網路光電技術開發---總計畫(I) 2006
25 奈米CMOS之前瞻射頻類比電路設計-總計畫(I) 2005
26 奈米CMOS之前瞻射頻類比電路設計-子計畫二：奈米CMOS射頻類比電路之可靠度設計與研究(1I)
 2005
27 高性能混合訊號式介面積體電路-子計畫二：射頻電路之靜電放電防護技術與高速高低壓界面電路之研發(III) 2004
28 高性能混合訊號式介面積體電路---子計畫II---射頻電路之靜電放電防護技術與高速高低壓界面電路之研發(II)
 2003
29 高性能混合訊號式介面積體電路---子計劃II：射頻電路之靜電放電防護技術與高速高低壓界面電路之研發(I)
 2002
30 適用於GHz頻段之輸出入靜電放電防護技術與銲墊設計
 2001
31 深次微米互補式金氧半製程技術下之混合電壓輸出入界面電路與靜電放電防護電路的設計
 2000

Proceedings Paper

序號
No.		 標題
Title		 著作日期
Date
1 Study on ESD Protection Design with Stacked Low-Voltage Devices for High-Voltage Applications 2014-01-01
2 Self-Protected LDMOS Output Device with Embedded SCR to Improve ESD Robustness in 0.25-mu m 60-V BCD Process 2013-01-01
3 Investigation on Safe Operating Area and ESD Robustness in a 60-V BCD Process with Different Deep P-Well Test Structures 2013-01-01
4 Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology 2013-01-01
5 Analysis and Solution to Overcome EOS Failure Induced by Latchup Test in A High-Voltage Integrated Circuits 2013-01-01
6 New Design of Transient-Noise Detection Circuit with SCR Device for System-Level ESD Protection 2012-01-01
7 High-Voltage-Tolerant Stimulator with Adaptive Loading Consideration for Electronic Epilepsy Prosthetic SoC in a 0.18-mu m CMOS Process 2012-01-01
8 ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process 2012-01-01
9 Design of ESD Protection Cell for Dual-Band RF Applications in a 65-nm CMOS Process 2012-01-01
10 Failure Analysis on Gate-Driven ESD Clamp Circuit after TLP Stresses of Different Voltage Steps in a 16-V CMOS Process 2012-01-01
11 Design of ESD Protection for RF CMOS Power Amplifier with Inductor in Matching Network 2012-01-01
12 Design of Negative High Voltage Generator for Biphasic Stimulator with SoC Integration Consideration 2012-01-01
13 Live Demonstration: Implantable Stimulator for Epileptic Seizure Suppression with Loading Impedance Adaptability 2012-01-01
14 Compact and Low-Loss ESD Protection Design for V-Band RF Applications in a 65-nm CMOS Technology 2012-01-01
15 Impact of Shielding Line on CDM ESD Robustness of Core Circuits in a 65-nm CMOS Process 2011-01-01
16 Design and Implementation of Capacitive Sensor Readout Circuit on Glass Substrate for Touch Panel Applications 2011-01-01
17 Layout Styles to Improve CDM ESD Robustness of Integrated Circuits in 65-nm CMOS Process 2011-01-01
18 On-chip detection circuit for protection design in display panel against electrical fast transient (EFT) disturbance
 2011-01-01
19 ESD-Aware Circuit Design in CMOS Integrated Circuits to Meet System-Level ESD Specification in Microelectronic Systems 2011-01-01
20 Design of Mixed-Voltage-Tolerant Crystal Oscillator Circuit in Low-Voltage CMOS Technology
 2009-05-01
21 Transient-to-Digital Converter for Protection Design in CMOS Integrated Circuits against Electrical Fast Transient 2009-01-01
22 Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection 2009-01-01
23 Design of 2xVDD-Tolerant I/O Buffer with 1xVDD CMOS Devices 2009-01-01
24 Circuit Solutions on ESD Protection Design for Mixed-Voltage I/O Buffers in Nanoscale CMOS 2009-01-01
25 Low-Leakage Electrostatic Discharge Protection Circuit in 65-nm Fully-Silicided CMOS Technology 2009-01-01
26 Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in Nanoscale Low-Voltage CMOS Process 2009-01-01
27 DESIGN OF ON-CHIP POWER-RAIL ESD CLAMP CIRCUIT WITH ULTR-SMALL CAPACITANCE TO DETECT ESD TRANSITION 2009-01-01
28 Design and Realization of Delta-Sigma Analog-to-Digital Converter in LTPS Technology 2009-01-01
29 Investigation and Design of On-Chip Power-Rail ESD Clamp Circuits Without Suffering Latchup-Like Failure During System-Level ESD Test
 2008-11-01
30 Active ESD Protection Design for Interface Circuits Between Separated Power Domains Against Cross-Power-Domain ESD Stresses
 2008-09-01
31 Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
 2008-05-01
32 Optimization on SCR device with low capacitance for on-chip ESD protection in UWB RF circuits 2008-01-01
33 Design of Bandgap Voltage Reference Circuit with all TFT Devices on Glass Substrate in a 3-mu m UPS Process 2008-01-01
34 CDM ESD Protection in CMOS Integrated Circuits 2008-01-01
35 Transient-to-Digital Converter for ESD Protection Design in Microelectronic Systems 2008-01-01
36 Transient Detection Circuit for System-Level ESD Protection and Its On-Board Behavior with EMI/EMC Filters 2008-01-01
37 New transient detection circuit for system-level ESD protection
 2008-01-01
38 An ESD-Protected 5-GHz Differential Low-Noise Amplifier in a 130-nm CMOS Process 2008-01-01
39 Temperature coefficient of diode-connected LTPS poly-Si TFTs and its application on the bandgap reference circuit 2008-01-01
40 Active ESD protection circuit design against charged-device-model ESD event in CMOS integrated circuits
 2007-09-01
41 Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology
 2007-01-01
42 Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
 2007-01-01
43 On-panel analog output buffer for data driver with consideration of device characteristic variation in LTPS technology 2007-01-01
44 On-panel electrostatic discharge (ESD) protection design with thin-film transistor in LTPS process 2007-01-01
45 Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution 2007-01-01
46 Optimization of PMOS-triggered SCR devices for on-chip ESD protection in a 0.18-mu m CMOS technology 2007-01-01
47 The impact of N-drift implant on ESD robustness of high-voltage NMOS with embedded SCR structure in 40-V CMOS process 2007-01-01
48 Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test 2007-01-01
49 Design of 2xVDD-tolerant I/O buffer with considerations of gate-oxide reliability and hot-carrier degradation
 2007-01-01
50 A new architecture for charge pump circuit without suffering gate-oxide reliability in low-voltage CMOS processes
 2007-01-01
51 Design of high-voltage-tolerant power-rail ESD clamp circuit in low-voltage CMOS processes
 2007-01-01
52 Failure of on-chip power-fall ESD clamp circuits during system-level ESD test
 2007-01-01
53 Latchup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test 2007-01-01
54 Ultra low-capacitance bond pad for RF applications in CMOS technology
 2007-01-01
55 Design on mixed-voltage I/O buffers with consideration of hot-carrier reliability 2007-01-01
56 Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices
 2006-11-01
57 Optimization of broadband RF performance and ESD robustness by pi-model distributed ESD protection scheme
 2006-02-01
58 On-chip transient detection circuit for system-level ESD protection in CMOS ICs
 2006-01-01
59 Low-power wordline voltage generator for low-voltage flash memory
 2006-01-01
60 The impact of inner pickup on ESD robustness of multi-finger NMOS in nanoscale CMOS technology
 2006-01-01
61 Design on new tracking circuit of I/O buffer in 0.13-mu m cell library for mixed-voltage application 2006-01-01
62 ESD (Electrostatic Discharge) protection design for nanoelectronics in CMOS technology 2006-01-01
63 Gate-oxide reliability on CMOS analog amplifiers in a 130-nm low-voltage CMOS processes 2006-01-01
64 Dummy-gate structure to improve ESD robustness in a fully-salicided 130-nm CMOS technology without using extra salicide-bloc king mask 2006-01-01
65 Method to evaluate Cable Discharge Event (CDE) reliability of integrated circuits in CMOS technology 2006-01-01
66 ESD protection design for CMOS integrated circuits with mixed-voltage I/O interfaces 2006-01-01
67 System-level ESD protection design with on-chip transient detection circuit
 2006-01-01
68 Study of board-level noise filters to prevent transient-induced latchup in CMOS integrated circuits during EMC/ESD test 2006-01-01
69 ESC robustness of 40-V CMOS devices with/without drift implant
 2006-01-01
70 Experimental evaluation and device simulation of device structure influences on latchup immunity in high-voltage 40-V CMOS process
 2006-01-01
71 Dependence of layout parameters on CDE (Cable Discharge Event) robustness of CMOS devices in a 0.25-mu m salicided CMOS process 2006-01-01
72 Circuit performance degradation of sample-and-hold amplifier due to gate-oxide overstress in a 130-nm CMOS process
 2006-01-01
73 ESD protection design for 1-to 10-GHz distributed amplifier in CMOS technology
 2005-09-01
74 Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
 2005-09-01
75 Investigation on seal-ring rules for IC product reliability in 0.25-mu m CMOS technology
 2005-09-01
76 Decreasing-size distributed ESD protection scheme for broad-band RF circuits
 2005-02-01
77 On-chip high-voltage charge pump circuit in standard CMOS processes with polysilicon diodes
 2005-01-01
78 ESD protection design for mixed-voltage I/O interfaces - Overview 2005-01-01
79 Methodology to evaluate the robustness of integrated circuits under Cable Discharge Event 2005-01-01
80 Evaluation on efficient measurement setup for transient-induced latchup with bi-polar trigger 2005-01-01
81 Impact of MOSFET gate-oxide reliability on CMOS operational amplifiers in a 130-nm low-voltage CMOS process 2005-01-01
82 Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process 2005-01-01
83 Design on mixed-voltage I/O buffer with blocking NMOS and dynamic gate-controlled circuit for high-voltage-tolerant applications 2005-01-01
84 New curvature-compensation technique for CMOS bandgap reference with sub-1-v operation 2005-01-01
85 ESD protection structure with embedded high-voltage p-type SCR for automotive vacuum-fluorescent-display (VFD) applications 2005-01-01
86 Initial-on ESD protection design with PMOS-triggered SCR device
 2005-01-01
87 Self-substrate-triggered technique to enhance turn-on uniformity of multi-finger ESD protection devices 2005-01-01
88 Methods to improve machine-model ESD robustness of NMOS devices in fully-salicided CMOS technology 2005-01-01
89 Abnormal ESD failure mechanism in high-pin-count BGA packaged ICs due to stressing nonconnected balls
 2004-03-01
90 Transient-induced latchup in CMOS technology: Physical mechanism and device simulation 2004-01-01
91 A new output buffer for 3.3-V PCI-X application in a 0.13-mu m 1/2.5-V 2004-01-01
92 ESD protection design for broadband RF circuits with decreasing-size distributed protection scheme 2004-01-01
93 Characterization on ESD devices with test structures in silicon germanium RF BiCMOS process 2004-01-01
94 Test structures to verify ESD robustness of on-glass devices in UPS technology 2004-01-01
95 Correlation between transmission-line-pulsing I-V curve and human-body-model ESD level on low temperature poly-Si TFT devices 2004-01-01
96 Layout optimization on low-voltage-triggered PNP devices for ESD protection in mixed-voltage I/O interfaces 2004-01-01
97 Low-voltage-triggered PNP devices for ESD protection design in mixed-voltage I/O interface with over-VDD and under-VSS signal levels 2004-01-01
98 Design to avoid the over-gate-driven effect on ESD protection circuits in deep-submicron CMOS processes 2004-01-01
99 Native-NMOS-triggered SCR (NANSCR) for ESD protection in 0.13-mu m CMOS integrated circuits 2004-01-01
100 Analysis and prevention on NC-ball induced ESD damages in a 683-pin BGA packaged chipset IC
 2003-09-01
101 Interference of esd protection diodes on RF performance in GIGA-HZ RF circuits 2003-01-01
102 A novel LC-Tank ESD protection design for giga-Hz RF circuits 2003-01-01
103 Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's 2003-01-01
104 ESD protection design for mixed-voltage-tolerant I/O buffers with substrate-triggered technique 2003-01-01
105 Design of 2.5V/5V mixed-voltage CMOS I/O buffer with only thin oxide device and dynamic N-well bias circuit 2003-01-01
106 MOS-bounded diodes for on-chip ESD protection in a 0.15-mu m shallow-trench-isolation salicided CMOS process 2003-01-01
107 Evaluation on ESD robustness of UPS diode and TFT device by transmission line pulsing (TLP) technique 2003-01-01
108 Novel electrostatic discharge protection design for nanoelectronics in nanoscale CMOS technology 2003-01-01
109 Electrostatic discharge implantation to improve machine-model ESD robustness of stacked NMOS in mixed-voltage I/O interface circuits 2003-01-01
110 Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications
 2002-09-01
111 Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution 2002-01-01
112 Complementary substrate-triggered SCR devices for on-chip ESD protection circuits 2002-01-01
113 ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness 2002-01-01
114 ESD protection design for 900-MHz RF receiver with 8-kV HBM ESD robustness 2002-01-01
115 ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process 2002-01-01
116 Novel ESD implantation for sub-quarter-micron CMOS technology with enhanced machine-model ESD robustness 2002-01-01
117 ESD protection design to overcome internal damages on interface circuits of CMOS IC with multiple separated power pins 2002-01-01
118 Design of negative charge pump circuit with polysilicon diodes in a 0.25-mu m CMOS process 2002-01-01
119 On-chip ESD protection circuit design with novel substrate-triggered SCR device in sub-quarter-micron CMOS process 2002-01-01
120 ESD protection circuits with novel MOS-bounded diode structures 2002-01-01
121 Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits 2002-01-01
122 Layout design to minimize voltage-dependent variation on input capacitance of an analog ESD protection circuit
 2002-01-01
123 Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process 2001-01-01
124 Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology 2001-01-01
125 ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration 2001-01-01
126 Novel diode structures and ESD protection circuits in a 1.8-V 0.15-mu m partially-depleted SOI salicided CMOS process 2001-01-01
127 Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's 2001-01-01
128 ESD test methods on integrated circuits: An overview 2001-01-01
129 Design on ESD protection circuit with very low and constant input capacitance 2001-01-01
130 Compact layout rule extraction for latchup prevention in a 0.25-mu m shallow-trench-isolation silicided bulk CMOS process 2001-01-01
131 Investigation on ESD robustness of CMOS devices in a 1.8-v 0.15-mu m partially-depleted SOI salicide CMOS technology 2001-01-01
132 ESD protection strategy for sub-quarter-micron CMOS technology: Gate-driven design versus substrate-triggered design 2001-01-01
133 Level shifters for high-speed 1-v to 3.3-v interfaces in a 0.13-mu m Cu-Interconnection/Low-k CMOS technology 2001-01-01
134 New diode string design with very low leakage current for using in power supply ESD clamp circuits 2000-01-01
135 Design and analysis of the on-chip ESD protection circuit with a constant input capacitance for high-precision analog applications 2000-01-01
136 Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits 2000-01-01
137 Novel input ESD protection circuit with substrate-triggering technique in a 0.25-mu m shallow-trench-isolation CMOS technology 1998-01-01
138 Efficient layout style of cmos output buffer to improve driving capability of low-voltage submicron cmos IC's 1995-01-01
139 Complementary-LVTSCR ESD protection scheme for submicron CMOS IC's 1995-01-01
140 AN ON-CHIP ESD PROTECTION CIRCUIT WITH COMPLEMENTARY SCR STRUCTURES FOR SUBMICRON CMOS ICS 1994-01-01

Thesis

序號
No.		 標題
Title		 著作日期
Date
1 使用低壓元件堆疊來達成高壓積體電路之靜電放電防護設計 2014
2 抑制癲癇發作之電荷平衡電流刺激器設計 2014
3 高介電係數 /金屬閘極製程之靜電放電防護設計與研究 2014
4 具有正負電壓極性之抑制癲癇發作雙向電流刺激器設計 2013
5 系統單晶片應用之靜電放電箝制電路與輸出緩衝器可靠度設計 2013
6 奈米互補式金氧半製程下應用於射頻積體電路之靜電放電防護設計 2013
7 運用在人工耳蝸的雙向雙極性電壓刺激器設計 2013
8 高壓製程之靜電放電防護元件設計 2013
9 全金屬矽化物互補式金氧半奈米晶片之靜電放電防護電路設計與實現 2012
10 高壓製程之靜電放電防護設計
 2012
11 Design of Biphasic Stimulus Driver to Suppress Epileptic Seizure and Negative High Voltage Generator in the Low Voltage Process
 2012
12 應用於射頻積體電路之靜電放電防護設計
 2012
13 高壓製程積體電路之靜電放電防護設計與應用
 2011
14 低溫多晶矽製程之畫素記憶體電路暨數位類比轉換器電路設計與實現
 2011
15 利用矽控整流器當做記憶單元之系統層級靜電放電暫態偵測電路
 2011
16 玻璃基板上之電路設計與實現及其於顯示系統之應用 2011
17 低溫多晶矽製程之類比積體電路設計與實現 2010
18 應用於低溫多晶矽製程下電容式感測器讀出電路設計與實現 2010
19 積體電路元件充電模式之靜電放電防護設計
 2010
20 具有負載適應性之抑制癲癇發作電流刺激器設計 2010
21 奈米互補式金氧半製程下之低漏電電源箝制靜電放電防護電路設計
 2010
22 高壓製程靜電放電防護元件設計與其安全操作範圍之研究
 2010
23 可相容高工作電壓且具有負載適應性之抑制癲癇發作電流刺激器設計
 2010
24 積體電路電源線間具低漏電流之靜電放電防護電路設計
 2009
25 高壓BCD製程之靜電放電防護元件設計與實現
 2009
26 提昇多指狀靜電放電保護元件導通均勻度之設計
 2009
27 利用一倍供應電壓元件實現兩倍供應電壓共容輸入輸出緩衝器設計
 2009
28 積體電路產品之元件充電模式靜電放電測試與研究
 2009
29 90奈米互補式金氧半製程下之多功能輸入/輸出元件庫設計
 2008
30 抑制熱載子劣化效應與閘極氧化層過壓之混合電壓輸入輸出緩衝器設計
 2008
31 應用於低溫多晶矽製成下和差類比數位轉換器電路設計與實現
 2008
32 低電壓製程之電荷幫浦電路設計
 2008
33 擴散電阻的靜電放電特性分析與防護設計上的應用
 2008
34 射頻電路與高速輸入輸出界面電路之靜電放電防護設計
 2008
35 全金屬矽化物互補式金氧半製程之矽控整流器及其在射頻電路之靜電放電防護設計與應用
 2008
36 互補式金氧半積體電路靜電放電防護之設計最佳化與故障分析
 2008
37 互補式金氧半積體電路之系統層級靜電放電防護設計
 2008
38 高壓製程之靜電放電防護元件設計
 2007
39 低溫複晶矽面板上之靜電放電耐受度研究
 2007
40 Design of On-Chip Transient Detection Circuits for System-Level ESD Protection
 2007
41 Temperature Coefficient Model of Poly-Silicon TFT and its Application on Voltage Reference Circuit with Temperature Compensation in LTPS process
 2007
42 奈米互補式金氧半製程下之低漏電源箝制靜電放電防護電路
 2007
43 平面顯示器玻璃基板上具有位階轉換功能之類比輸出級電路設計
 2007
44 低電壓互補式金氧半製程下可相容高工作電壓之靜電放電防護設計
 2007
45 低電壓互補式金氧半製程下的類比電路設計與可靠度
 2007
46 射頻功率放大器之靜電放電防護設計
 2007
47 用低壓元件實現之混合電壓共容石英振盪電路設計
 2006
48 高速輸出入介面電路之靜電放電防護設計
 2006
49 應用於薄膜電晶體之平面顯示器玻璃基底上的類比電路設計
 2006
50 系統層級靜電放電測試下之積體電路暫態觸發閂鎖效應
 2005
51 系統層級靜電放電感測器設計
 2005
52 增強靜電放電保護元件導通均勻度之設計
 2005
53 長脈衝傳輸線觸波技術及其在積體電路電纜放電防護上之應用
 2005
54 具有電壓迴轉率控制之混合式電壓輸入/輸出緩衝器設計
 2005
55 低電壓製程之電荷幫浦電路設計
 2005
56 低電壓互補式金氧半製程下的高電壓電路設計
 2005
57 具基體雜訊考量之射頻電壓控制振盪器電路設計
 2004
58 矽鍺製程之低漏電流二極體串聯電路及其在靜電放電防護上之應用
 2004
59 考量閘極可靠度之晶片上靜電放電防護電路設計
 2004
60 具有SSTL_2規格之高速輸入/輸出電路設計及分析
 2004
61 低電壓差動訊號傳輸標準之平面顯示器資料接收器設計
 2004
62 低壓差動訊號標準(LVDS)之平面顯示器高速傳送器設計
 2004
63 適用於高低壓共容輸入輸出介面之積體電路靜電放電防護設計
 2004
64 具有 LVDS 與 RSDS 低電壓差動訊號傳輸規格之平面顯示器高速輸入輸出緩衝器設計
 2003
65 低溫複晶矽玻璃基板上之液晶顯示器驅動電路設計
 2003
66 矽化金屬互補式金氧半導體製程之新型靜電放電防護元件
 2003
67 射頻互補式金氧半導體低雜訊放大器之靜電放電防護設計 2002
68 低電壓能帶隙參考電壓產生器之設計 2002
69 高速應用之傳輸電路設計 2002
70 高低壓混合輸入輸出介面之設計 2002
71 應用低溫多晶矽製程實現之液晶顯示器驅動電路 2002
72 閘極耦合靜電放電防護電路之最佳化設計與驗証 2002
73 應用於定位系統之相位對數位轉換器 2002
74 基體觸發技術與積體電路晶片上之靜電放電防護電路設計 2001
75 提升機械模式靜電放電防護能力之元件結構設計 2001
76 薄膜電晶體液晶顯示器驅動電路之設計 2001
77 高速輸出輸入介面之電路設計 2001
78 積體電路之高可靠度與低寄生電容銲墊設計 2001
79 八位元互補式金氧半溫度至數位轉換器之設計 2000
80 深次微米互補式金氧半靜電放電防護佈植及新型二極體結構設計 2000
81 絕緣層上有矽互補式金氧半製程技術 2000
82 適用於高低壓共容輸入輸出電路之靜電放電防護設計 2000
83 功率積體電路之靜電放電防護設計實例 1999
84 互補式金氧半積體電路之靜電放電保護電路及低同步切換雜訊輸出驅動級之設計 1998
85 防制閂鎖效應的佈局準則訂定及靜電放電保護用電源箝制電路之設計 1998
86 互補式金氧半暫態鎖住效應及晶片上靜電放電保護電路之研究. 1993
87 互補式金氧半傳輸閘之時序模式及其應用 1987
電機學院