1. 目前位置：
郭治群

郭治群 Guo, Jyh-Chyurn

電子郵件／E-mail：jcguo@mail.nctu.edu.tw

服務單位／Department：電機學院 ／ 電子工程學系及電子研究所

著作期間／Publish Period：1993 - 2014-03-11

著作統計／Statistics

Article（22）
Books（1）
Others（1）
Patents（2）
Plan（14）
Proceedings Paper（17）
Thesis（18）

Article

序號
No.		 標題
Title		 著作日期
Date
1 Narrow-Width Effect on High-Frequency Performance and RF Noise of Sub-40-nm Multifinger nMOSFETs and pMOSFETs
 2013-01-01
2 A New Method for Layout-Dependent Parasitic Capacitance Analysis and Effective Mobility Extraction in Nanoscale Multifinger MOSFETs
 2011-09-01
3 Layout-Dependent Stress Effect on High-Frequency Characteristics and Flicker Noise in Multifinger and Donut MOSFETs
 2011-09-01
4 The Impact of Layout-Dependent STI Stress and Effective Width on Low-Frequency Noise and High-Frequency Performance in Nanoscale nMOSFETs
 2010-11-01
5 The Impact of Uni-axial Strain on Low Frequency Noise in Nanoscale p-Channel Metal-Oxide-Semiconductor Field Effect Transistors under Dynamic Body Biases
 2010-08-01
6 The Impact of Uniaxial Strain on Low Frequency Noise of Nanoscale PMOSFETs with e-SiGe and i-SiGe Source/Drain 2010-01-01
7 The Impact of MOSFET Layout Dependent Stress on High Frequency Characteristics and Flicker Noise
 2010-01-01
8 A New Three-Dimensional Capacitor Model for Accurate Simulation of Parasitic Capacitances in Nanoscale MOSFETs
 2009-08-01
9 A Broadband and Scalable Lossy Substrate Model for RF Noise Simulation and Analysis in Nanoscale MOSFETs With Various Pad Structures
 2009-02-01
10 A compact RF CMOS modeling for accurate high-frequency noise simulation in sub-100-nm MOSFETs
 2008-09-01
11 A simple analytical model to accurately predict self-resonance frequencies of on-silicon-chip inductors in TEM mode and eddy current mode
 2008-08-01
12 A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities
 2007-11-01
13 A broadband and scalable lumped element model for fully symmetric inductors under single-ended and differentially driven operations
 2007-08-01
14 A scalable lossy substrate model for nanoscale RF MOSFET noise extraction and simulation adapted to various pad structures
 2007-01-01
15 A new lossy substrate model for accurate RF CMOS noise extraction and simulation with frequency and bias dependence
 2006-11-01
16 Low-K/Cu CMOS-based SoC technology with 115-GHz f(T), 100-GHz f(max), noise 80-nm RF CMOS, high-Q MiM capacitor, and spiral Cu inductor
 2006-08-01
17 A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects
 2006-03-01
18 A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling
 2006-02-01
19 0.13-mu m RF CMOS and varactors performance optimization by multiple gate layouts
 2004-12-01
20 Pocket implantation effect on drain current flicker noise in analog nMOSFET devices
 2004-08-01
21 0.13-mu m low-kappa-Cu CMOS logic-based technology for 2.1-Gb high data rate read-channel
 2004-05-01
22 TRANSCONDUCTANCE ENHANCEMENT DUE TO BACK BIAS FOR SUBMICRON NMOSFET
 1995-02-01

Books

序號
No.		 標題
Title		 著作日期
Date
1 國立交通大學電子工程學系郭治群教師升等送審著作論文集 2008

Others

序號
No.		 標題
Title		 著作日期
Date
1 The Impact of Uniaxial Strain on Low Frequency Noise of Nanoscale PMOSFETs with e-SiGe and i-SiGe Source/Drain 2010-01-01

Patents

序號
No.		 標題
Title		 著作日期
Date
1 半導體元件之參數萃取方法
 2014-03-11
2 半導體元件之參數萃取方法
 2012-08-01

Plan

序號
No.		 標題
Title		 著作日期
Date
1 奈米CMOS模型研發以探討應力工程與佈局效應對於高頻特性與寬頻雜訊之影響(III) 2014
2 奈米CMOS模型研發以探討應力工程與佈局效應對於高頻特性與寬頻雜訊之影響(II) 2013
3 奈米CMOS模型研發以探討應力工程與佈局效應對於高頻特性與寬頻雜訊之影響(I) 2012
4 奈米CMOS射頻與混合訊號模型研發應用於超低功耗設計 2011
5 奈米CMOS射頻與混合訊號模型研發應用於超低功耗設計 2010
6 奈米CMOS射頻與混合訊號模型研發應用於超低功耗設計 2009
7 奈米CMOS之高性能類比數位混合信號關鍵電路設計技術---子計畫一：奈米CMOS射頻與混合訊號模型研發應用於超低功耗與低雜訊設計 2008
8 奈米CMOS之前瞻射頻類比電路設計---子計畫一：奈米CMOS高頻與類比元件模型研發(III)
 2007
9 奈米CMOS之前瞻射頻類比電路設計---子計畫一：奈米CMOS高頻與類比元件模型研發(II) 2006
10 低功率系統之設計及自動化-子計畫五：低耗功率CMOS射頻積體電路(III) 2005
11 奈米CMOS之前瞻射頻類比電路設計-子計畫一：奈米CMOS高頻與類比元件模型研發(I) 2005
12 低功率系統之設計及自動化-子計畫五：低耗功率CMOS射頻積體電路(II) 2004
13 低雜訊與低耗功率之CMOS射頻元件與電路技術
 2003
14 低功率系統之設計及自動化---子計畫V：低耗功率CMOS射頻積體電路(I) 2003

Proceedings Paper

序號
No.		 標題
Title		 著作日期
Date
1 Low Frequency Noise in Nanoscale pMOSFETs with Strain Induced Mobility Enhancement and Dynamic Body Biases
 2009-01-01
2 Flicker Noise in Nanoscale pMOSFETs with Mobility Enhancement Engineering and Dynamic Body Biases 2009-01-01
3 RF Noise Shielding Method and Modelling for Nanoscale MOSFET
 2008-01-01
4 Broadband and scalable on-silicon-chip inductor model for varying substrate resistivities 2006-01-01
5 65-nm 160-GHz f(T) RF n-MOSFET intrinsic noise extraction and modeling using lossy substrate de-embedding method 2006-01-01
6 A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities 2006-01-01
7 65-nm 160-GHz f(T) RF n-MOSFET intrinsic noise extraction and modeling using lossy substrate de-embedding method 2006-01-01
8 A broadband and scalable on-chip inductor model appropriate for operation modes of varying substrate resistivities 2006-01-01
9 P-channel SONOS transient current modeling for program and erase 2006-01-01
10 Low-power and high-linearity mixer design using complex transconductance equivalent circuit 2005-01-01
11 A lossy substrate model for sub-100nm, super-100 GHz f(T) RF CMOS noise extraction and modeling 2005-01-01
12 A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects 2005-01-01
13 A simple transmission line de-embedding method for accurate RF CMOS noise modeling
 2004-01-01
14 0.13 mu m low voltage logic based RF CMOS technology with 115GHz f(T) and 80GHz f(MAX) 2003-01-01
15 Mechanisms and characteristics of oxide charge detrapping in n-MOSFET's 1996-01-01
16 Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement results
 1995-01-01
17 DIRECT OBSERVATION OF CHANNEL-DOPING-DEPENDENT REVERSE SHORT-CHANNEL EFFECT USING DECOUPLED C-V TECHNIQUE
 1994-01-01

Thesis

序號
No.		 標題
Title		 著作日期
Date
1 低功耗CMOS超寬頻與毫米波低雜訊放大器之分析與設計 2014
2 Small Signal Equivalent Circuit Models Development and Verification for Four-port RF MOSFET and New Cascode Structure with Merged Source Drain Diffusion
 2011
3 射頻金氧半場效電晶體元件佈局對高頻特性與低頻雜訊之影響以應用於射頻與類比電路
 2010
4 基板雜訊隔離結構設計與分析以應用於射頻與類比電路 2010
5 低功耗與超寬頻射頻CMOS混頻器設計與分析 2010
6 低功耗壓控振盪器設計與順向基極偏壓之應用 2010
7 奈米金氧半電晶體佈局對高頻特性與雜訊之影響以及低功耗超寬頻低雜訊放大器之設計應用 2010
8 利用順向基極偏壓設計之低功耗低雜訊放大器
 2009
9 射頻金氧半電晶體小訊號等效電路模型參數萃取方法建立以應用於各種偏壓與幾何結構
 2008
10 單晶片寬頻電感設計以及等效電路模擬及分析
 2008
11 5.5GHz 低功耗射頻 CMOS混頻器設計與研製
 2006
12 損耗基板模型建立與高頻雜訊模擬射頻場效電晶體與探針墊結構之研究
 2006
13 低電壓能帶隙參考電壓產生器之設計
 2005
14 三端點與四端點的射頻金氧半電晶體模型參數萃取方法之建立及等效電路模擬之驗證
 2005
15 損耗基板之去寄生效應法與射頻金氧半場效電晶體雜訊萃取之應用
 2005
16 單晶片電感模型研發及射頻積體電路模擬與設計方面之應用
 2005
17 四極射頻金氧半電晶體於雙埠量測下的去寄生效應方法與參數萃取之研究
 2004
18 小型化金氧半場效電晶體之新的參數擷取法與模式之建立 1993
電機學院