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莊景德

莊景德 Chuang, Ching-Te

電子郵件／E-mail：ctchuang@mail.nctu.edu.tw

服務單位／Department：其他 ／ 奈米電子與系統研究中心

著作期間／Publish Period：1996-10-07 - 2014-12-11

著作統計／Statistics

Article（44）
Patents（25）
Plan（7）
Proceedings Paper（36）
Thesis（24）

Article

序號
No.		 標題
Title		 著作日期
Date
1 Stability and Performance Optimization of Heterochannel Monolithic 3-D SRAM Cells Considering Interlayer Coupling 2014-10-01
2 40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
 2014-09-01
3 Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration
 2014-04-01
4 Single-trap-induced random telegraph noise for FinFET, Si/Ge Nanowire FET, Tunnel FET, SRAM and logic circuits
 2014-04-01
5 Low-Power Multiport SRAM With Cross-Point Write Word-Lines, Shared Write Bit-Lines, and Shared Write Row-Access Transistors
 2014-03-01
6 A TSV-Based Bio-Signal Package With mu-Probe Array
 2014-02-01
7 Novel Cu-to-Cu Bonding With Ti Passivation at 180 degrees C in 3-D Integration
 2013-12-01
8 Comparative Leakage Analysis of GeOI FinFET and Ge Bulk FinFET
 2013-10-01
9 Slew-Rate Monitoring Circuit for On-Chip Process Variation Detection
 2013-09-01
10 Threshold Voltage Design of UTB SOI SRAM With Improved Stability/Variability for Ultralow Voltage Near Subthreshold Operation
 2013-07-01
11 Analysis of Single-Trap-Induced Random Telegraph Noise and its Interaction With Work Function Variation for Tunnel FET
 2013-06-01
12 Design and Analysis of Robust Tunneling FET SRAM
 2013-03-01
13 Threshold Voltage Design and Performance Assessment of Hetero-Channel SRAM Cells
 2013-01-01
14 A 0.33-V, 500-kHz, 3.94-mu W 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist
 2012-12-01
15 Variability Analysis of Sense Amplifier for FinFET Subthreshold SRAM Applications 2012-12-01
16 A Band-Notched UWB Monopole Antenna With High Notch-Band-Edge Selectivity
 2012-10-01
17 "Analysis of Single-Trap-Induced Random Telegraph Noise on FinFET Devices, 6T SRAM Cell, and Logic Circuits" 2012-08-01
18 Independently-Controlled-Gate FinFET Schmitt Trigger Sub-Threshold SRAMs
 2012-07-01
19 A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing
 2012-06-01
20 Band-to-Band-Tunneling Leakage Suppression for Ultra-Thin-Body GeOI MOSFETs Using Transistor Stacking
 2012-02-01
21 A Compact Printed Filtering Antenna Using a Ground-Intruded Coupled Line Resonator
 2011-10-01
22 Analysis of Ultra-Thin-Body SOI Subthreshold SRAM Considering Line-Edge Roughness, Work Function Variation, and Temperature Sensitivity 2011-09-01
23 Impacts of NBTI/PBTI and Contact Resistance on Power-Gated SRAM With High-kappa Metal-Gate Devices
 2011-07-01
24 Impacts of NBTI/PBTI on Timing Control Circuits and Degradation Tolerant Design in Nanoscale CMOS SRAM
 2011-06-01
25 Synthesis and Design of a New Printed Filtering Antenna
 2011-03-01
26 Comparison of 4T and 6T FinFET SRAM Cells for Subthreshold Operation Considering Variability-A Model-Based Approach
 2011-03-01
27 FinFET SRAM Cell Optimization Considering Temporal Variability Due to NBTI/PBTI, Surface Orientation and Various Gate Dielectrics
 2011-03-01
28 Impacts of gate-oxide breakdown on power-gated SRAM
 2011-01-01
29 SRAM Write-Ability Improvement With Transient Negative Bit-Line Voltage 2011-01-01
30 Investigation of Cell Stability and Write Ability of FinFET Subthreshold SRAM Using Analytical SNM Model
 2010-06-01
31 FinFET SRAM Cell Optimization Considering Temporal Variability due to NBTI/PBTI and Surface Orientation 2010-01-01
32 Independently-Controlled-Gate FinFET Schmitt Trigger Sub-threshold SRAMs 2010-01-01
33 Evaluation of Static Noise Margin and Performance of 6T FinFET SRAM Cells with Asymmetric Gate to Source/Drain Underlap Devices 2010-01-01
34 TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability
 2009-12-01
35 Static Noise Margin of Ultrathin-Body SOI Subthreshold SRAM Cells-An Assessment Based on Analytical Solutions of Poisson's Equation
 2009-09-01
36 Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability
 2009-06-01
37 Design of Sub-90 nm Low-Power and Variation Tolerant PD/SOI SRAM Cell Based on Dynamic Stability Metrics
 2009-03-01
38 Selective Device Structure Scaling and Parasitics Engineering: A Way to Extend the Technology Roadmap
 2009-02-01
39 Asymmetrical Write-Assist for Single-Ended SRAM Operation 2009-01-01
40 Design and Analysis of Ultra-Thin-Body SOI Based Subthreshold SRAM 2009-01-01
41 Optimal design of triple-gate devices for high-performance and low-power applications
 2008-09-01
42 Intramolecular Diels-Alder reaction of furans with allenyl ethers followed by phenylthio and trialkylsilyl groups rearrangement 1998-12-01
43 Intramolecular Diels-Alder reaction of furans with allenyl ethers followed by sulfur and silicon atom-containing group rearrangement
 1998-07-24
44 Intramolecular Diels-Alder reaction of furans with allenyl ethers followed by trimethylsilyl group 1,2-rearrangement and Brook rearrangement
 1996-10-07

Patents

序號
No.		 標題
Title		 著作日期
Date
1 具有由資料控制之電源供應的靜態隨機存取記憶體
 2014-12-11
2 靜態記憶體及記憶胞
 2014-11-01
3 以史密特觸發器為基礎的鰭狀場效電晶體靜態隨機存取記憶體
 2014-10-01
4 可容忍閘極崩毀之功率閘結構
 2014-07-01
5 依據資料動態供電之隨機存取記憶體
 2014-03-21
6 靜態隨機存取記憶體
 2014-03-16
7 靜態隨機存取記憶體的控制電路及其操作方法
 2014-03-16
8 臨界電壓量測裝置
 2014-02-01
9 靜態隨機存取記憶裝置及其位元線電壓控制電路
 2014-01-16
10 靜態隨機存取記憶體裝置
 2013-12-11
11 高負載驅動裝置
 2013-12-01
12 臨界電壓量測裝置
 2013-11-16
13 靜態隨機存取記憶體
 2013-10-01
14 以六電晶體為基礎架構之靜態隨機記憶體陣列
 2013-09-01
15 用以量測偏壓溫度效應之環形震盪器
 2013-09-01
16 單端靜態隨機存取記憶體
 2013-08-16
17 獨立閘極控制靜態隨機存取記憶體
 2013-05-01
18 可容忍閘極崩毀之功率閘結構
 2012-04-16
19 依據資料動態供電之隨機存取記憶體
 2012-03-01
20 具容忍變異字元線驅動抑制機制之隨機存取記憶體
 2012-02-16
21 以史密特觸發器為基礎的鰭狀場效電晶體靜態隨機存取記憶體
 2012-02-01
22 具有由資料控制之電源供應的靜態隨機存取記憶體
 2012-01-16
23 低電能靜態隨機存取記憶體
 2012-01-16
24 高負載驅動裝置
 2012-01-01
25 靜態隨機存取記憶體裝置
 2011-02-01

Plan

序號
No.		 標題
Title		 著作日期
Date
1 穿隧場效電晶體及混合穿隧場效電晶體與金氧半場效電晶體的邏輯電路與靜態隨機存取記憶體之探索與評估 2014
2 超高通道與解析度微大腦皮質訊號擷取系統晶片封裝的研發---子計畫三：超高通道與解析度腦神經訊號擷取電路設計佈局及功耗優化 2014
3 前瞻多閘極/全包覆閘極、奈米線、及穿隧場效電晶體於靜態隨機存取記憶體、邏輯、類比應用之分析與評估 2013
4 前瞻多閘極/全包覆閘極、奈米線、及穿隧場效電晶體於靜態隨機存取記憶體、邏輯、類比應用之分析與評估 2012
5 奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計
 2011
6 奈米互補式金氧半場效電晶體靜態隨機存取記憶體靜態雜訊邊界與負偏壓溫度效應/正偏壓溫度效應之量測與特性化電路結構設計
 2010
7 奈米隨機存取記憶體的長時間可靠度劣化現象分析與可容忍此劣化現象之設計
 2009

Proceedings Paper

序號
No.		 標題
Title		 著作日期
Date
1 Investigation of Single-Trap-Induced Random Telegraph Noise for Tunnel FET Based Devices, 8T SRAM Cell, and Sense Amplifiers 2013-01-01
2 Device Design and Analysis of Logic Circuits and SRAMs for Germanium FinFETs on SOI and Bulk Substrates 2013-01-01
3 Analysis of Germanium FinFET Logic Circuits and SRAMs with Asymmetric Gate to Source/Drain Underlap Devices 2013-01-01
4 Design and Optimization of 6T SRAM using Vertically Stacked Nanowire MOSFETs 2013-01-01
5 Low Temperature (< 180 degrees C) Bonding for 3D Integration 2013-01-01
6 Impacts of Single Trap Induced Random Telegraph Noise on Si and Ge Nanowire FETs, 6T SRAM Cells and Logic Circuits 2013-01-01
7 Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection 2013-01-01
8 A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist 2013-01-01
9 Low Temperature (< 180 degrees C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration 2013-01-01
10 Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications 2013-01-01
11 Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications 2013-01-01
12 A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist 2013-01-01
13 Impacts of Random Telegraph Noise on FinFET Devices, 6T SRAM cell, and Logic Circuits 2012-01-01
14 Design and Implementation of Dynamic Word-Line Pulse Write Margin Monitor for SRAM 2012-01-01
15 A Comprehensive Comparative Analysis of FinFET and Trigate Device, SRAM and Logic Circuits 2012-01-01
16 Variation Tolerant CLSAs for Nanoscale Bulk-CMOS and FinFET SRAM 2012-01-01
17 High-Performance 0.6V V-MIN 55nm 1.0Mb 6T SRAM with Adaptive BL Bleeder 2012-01-01
18 An All-Digital Bit Transistor Characterization Scheme for CMOS 6T SRAM Array 2012-01-01
19 Testing Strategies for a 9T Sub-threshold SRAM 2012-01-01
20 Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration 2012-01-01
21 Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations 2012-01-01
22 Comprehensive Analysis of UTB GeOI Logic Circuits and 6T SRAM Cells considering Variability and Temperature Sensitivity 2011-01-01
23 A High-Performance Low V(MIN) 55nm 512Kb Disturb-Free 8T SRAM with Adaptive VVSS Control 2011-01-01
24 Impacts of Single Trap Induced Random Telegraph Noise on FinFET Devices and SRAM Cell Stability 2011-01-01
25 Single-Ended Subthreshold SRAM With Asymmetrical Write/Read-Assist
 2010-12-01
26 Energy Efficient Bootstrapped CMOS Large RC-Load Driver Circuit for Ultra Low-Voltage VLSI 2010-01-01
27 Impacts of NBTI on SRAM Array with Power Gating Structure 2009-01-01
28 Modeling, Analysis, and TCAD of Nanoscale Devices and Circuits 2009-01-01
29 Impacts of NBTI and PBTI on Power-Gated SRAM with High-k Metal-Gate Devices 2009-01-01
30 Investigation of Static Noise Margin of Ultra-Thin-Body SOI SRAM Cells in Subthreshold Region using Analytical Solution of Poisson's Equation 2009-01-01
31 New Printed Filtering Antenna with Selectivity Enhancement 2009-01-01
32 Impact of Gate-Oxide Breakdown on Power-Gated SRAM 2009-01-01
33 Investigation of Static Noise Margin of FinFET SRAM Cells in Sub-threshold Region 2009-01-01
34 Impacts of Contact Resistance and NBTI/PBTI on SRAM with High-kappa Metal-Gate Devices
 2009-01-01
35 TIMING CONTROL DEGRADATION AND NBTI/PBTI TOLERANT DESIGN FOR WRITE-REPLICA CIRCUIT IN NANOSCALE CMOS SRAM 2009-01-01
36 An on-chip test structure and digital measurement method for statistical characterization of local random variability in a process
 2008-09-01

Thesis

序號
No.		 標題
Title		 著作日期
Date
1 應用於高密度神經元感測之11位元低電壓面積與功耗最佳化之類比數位轉換器 2014
2 應用於低功率事件驅動感知平台之超低電壓全數位操控線性穩壓器 2014
3 40奈米製程技術操縱在低電壓的 256Kb 8T 雙埠隨機存取記憶體 2014
4 穿隧式場效電晶體與鰭式場效電晶體的隨機變異特性於元件及邏輯電路之研究與分析 2014
5 抗變異奈米互補式金氧半導體靜態隨機存取記憶體設計 2014
6 40奈米製程技術操縱在低操縱電壓的256-Kb 8T 靜態隨機存取記憶體 2013
7 應用於多通道神經感測之可配置小波離散轉換 2013
8 應用於2.5D異質整合生物感測微系統之矽載板資料傳輸 2013
9 鍺環繞閘極奈米線金氧半場效電晶體及無接面電晶體、邏輯電路和靜態隨機存取記憶體之研究與分析 2013
10 快速獨立成份分析於多重氣體感測器應用之低功耗演算法暨架構共同設計 2013
11 低操作電壓奈米級靜態隨機記憶體電路設計 2013
12 實現在40奈米製程下可操縱在低電壓的四讀四寫多執行序暫存器叢集設計 2012
13 奈米尺度多重閘極金氧半場效電晶體之靜態隨機存取記憶體的設計與分析特性 2012
14 鰭狀及三閘極場效電晶體元件、邏輯電路、類比電路和靜態隨機存取記憶體之研究與分析 2012
15 40奈米1.0Mb 6T管線化靜態隨機存取記憶體與三步階升壓型字元線和位元線降壓和適應性電壓偵測
 2012
16 40 奈米製程技術操縱在低操縱電壓及管線結構的512Kb 8T 靜態隨機存取記憶體 2012
17 應用於神經感測之面積與功耗最佳化11位元延遲線輔助之循序漸進式類比數位轉換器 2012
18 具高頻帶邊緣選擇之小型濾波天線 2011
19 40奈米1.0Mb 6T管線化靜態隨機存取記憶體與步階升壓型字元線和適應性數據感知寫入輔助設計 2011
20 奈米級CMOS靜態隨機存取記憶體之 臨界電壓量測電路 2011
21 史密特觸發器為基礎操作在次臨界區以獨立閘極控制場效鰭狀電晶體之靜態隨機存取記憶體 2010
22 6T靜態隨機存取記憶體的設計與特性分析 2010
23 應用於交叉點八電晶體靜態隨機存取記憶體之資料感知動態電源寫入輔助之分析與設計 2010
24 超低功率抗雜訊8T 靜態隨機存取記憶體的設計與實現
 2010
其他