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陳冠能

陳冠能 Chen, Kuan-Neng

電子郵件／E-mail：knchen@mail.nctu.edu.tw

服務單位／Department：電機學院 ／ 電子工程學系及電子研究所

著作期間／Publish Period：1980-01-01 - 2014-09-01

著作統計／Statistics

Article（39）
Books（1）
Others（1）
Patents（12）
Plan（8）
Proceedings Paper（12）
Thesis（14）

Article

序號
No.		 標題
Title		 著作日期
Date
1 Adhesion Investigation Between Metal and Benzocyclobutene (BCB) Polymer Dielectric Materials in 3-D Integration Applications
 2014-09-01
2 Conductivity enhancement of multiwalled carbon nanotube thin film via thermal compression method
 2014-08-29
3 Motional Resistance Issue of TSV-Based Resonator Device and Its Improvement With a Concave Cu TSV Structural Design
 2014-08-01
4 A Novel 3D Integration Scheme for Backside Illuminated CMOS Image Sensor Devices
 2014-06-01
5 Low-temperature direct copper-to-copper bonding enabled by creep on highly (111)-oriented Cu surfaces
 2014-05-01
6 Low-Temperature Bonded Cu/In Interconnect With High Thermal Stability for 3-D Integration
 2014-04-01
7 A precise pH microsensor using RF-sputtering IrO2 and Ta2O5 films on Pt-electrode
 2014-03-01
8 A TSV-Based Bio-Signal Package With mu-Probe Array
 2014-02-01
9 Novel Cu-to-Cu Bonding With Ti Passivation at 180 degrees C in 3-D Integration
 2013-12-01
10 Electrical Performance and Reliability Investigation of Cosputtered Cu/Ti Bonded Interconnects
 2013-10-01
11 Advanced TSV-Based Crystal Resonator Devices Using 3-D Integration Scheme With Hermetic Sealing
 2013-08-01
12 Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme
 2013-05-01
13 Backside-Process-Induced Junction Leakage and Process Improvement of Cu TSV Based on Cu/Sn and BCB Hybrid Bonding
 2013-03-01
14 Electrical and Reliability Investigation of Cu TSVs With Low-Temperature Cu/Sn and BCB Hybrid Bond Scheme
 2013-01-01
15 Reliability of key technologies in 3D integration
 2013-01-01
16 A Flexible pH-Sensing Structure Using WO3/IrO2 Junction with Al2O3 Encapsulation Layer
 2013-01-01
17 Al2O3 Interface Engineering of Germanium Epitaxial Layer Grown Directly on Silicon
 2013-01-01
18 Effects of Bonding Technology and Thinning Process in Three-Dimensional Integration on Device Characteristics 2012-10-01
19 Cosputtered Cu/Ti Bonded Interconnects With a Self-Formed Adhesion Layer for Three-Dimensional Integration Applications
 2012-07-01
20 A Wafer-Level Three-Dimensional Integration Scheme With Cu TSVs Based on Microbump/Adhesive Hybrid Bonding for Three-Dimensional Memory Application
 2012-06-01
21 Adhesive Selection and Bonding Parameter Optimization for Hybrid Bonding in 3D Integration 2012-03-01
22 Diffusion of Co-Sputtered Metals as Bonding Materials for 3D Interconnects During Thermal Treatments 2012-03-01
23 Low temperature bonding technology for 3D integration
 2012-02-01
24 Wafer-level Cu-Cu bonding technology
 2012-02-01
25 BCB-to-oxide bonding technology for 3D integration
 2012-02-01
26 Bonding Temperature Optimization and Property Evolution of SU-8 Material in Metal/Adhesive Hybrid Wafer Bonding 2011-08-01
27 Demonstration and Electrical Performance Investigation of Wafer-Level Cu Oxide Hybrid Bonding Schemes
 2011-08-01
28 Wafer-to-Wafer Alignment for Three-Dimensional Integration: A Review
 2011-08-01
29 Electrical Performances and Structural Designs of Copper Bonding in Wafer-Level Three-Dimensional Integration 2011-06-01
30 Integration schemes and enabling technologies for three-dimensional integrated circuits
 2011-05-01
31 Fabrication of Nano-Scale Cu Bond Pads with Seal Design in 3D Integration Applications 2011-04-01
32 Wafer-Level Self-Aligned Nano Tubular Structures and Templates for Device Applications 2010-12-01
33 Controlled large strain of Ni silicide/Si/Ni silicide nanowire heterostructures and their electron transport properties
 2010-11-15
34 Enhanced growth of low-resistivity titanium silicides on epitaxial Si(0.7)Ge(0.3) on (001)Si with a sacrificial amorphous Si interlayer 2010-10-01
35 The fabrication of a programmable via using phase-change material in CMOS-compatible technology
 2010-04-02
36 Reliability and structural design of a wafer-level 3D integration scheme with W TSVs based on Cu-oxide hybrid wafer bonding 2010-01-01
37 AN ACCURATE COMPUTATION FOR RAPIDLY VARIED FLOW IN AN OPEN CHANNEL
 1992-02-15
38 INVESTIGATION OF USE OF REACH-BACK CHARACTERISTICS METHOD FOR 2D DISPERSION-EQUATION
 1991-10-01
39 A SYSTEM APPROACH TO THE DYNAMIC CHARACTERISTICS OF HYDROSTATIC BEARINGS USED ON MACHINE-TOOLS 1980-01-01

Books

序號
No.		 標題
Title		 著作日期
Date
1 國立交通大學電子工程學系陳冠能教師升等送審著作論文集 2011

Others

序號
No.		 標題
Title		 著作日期
Date
1 Wafer-level three-dimensional integrated circuits (3D IC): Schemes and key technologies
 2011-11-01

Patents

序號
No.		 標題
Title		 著作日期
Date
1 三維積體電路
 2014-07-01
2 三維積體電路
 2014-07-01
3 具有積體電路與發光二極體之異質整合結構及其製作方法
 2014-04-11
4 三維積體電路之接合方法及其三維積體電路
 2014-04-01
5 晶圓次微米接合方法及其接合層
 2014-01-16
6 三維積體電路的靜電放電防護結構
 2013-11-21
7 立體積體電路裝置
 2013-07-16
8 三維積體電路之接合方法及其三維積體電路
 2013-04-01
9 三維積體電路
 2013-03-16
10 具有積體電路與發光二極體之異質整合結構及其製作方法
 2012-12-16
11 三維互補式金屬氧化物半導體元件
 2012-09-16
12 三維積體電路的靜電放電防護結構
 2012-07-01

Plan

序號
No.		 標題
Title		 著作日期
Date
1 發展超低溫銅接合與3DIC技術以實現40奈米與0.18微米異質整合平台及先進小尺寸石英震盪元件之研究 2014
2 超高通道與解析度微大腦皮質訊號擷取系統晶片封裝的研發---子計畫二：使用TSV與3D IC技術製作超高通道與解析度微大腦皮質訊號擷取系統晶片 2014
3 三維積體電路(3D IC)之記憶體元件堆疊設計、模擬、製程與電性量測研究(I) 2013
4 三維積體電路(3D IC)之矽晶直通孔(TSV)與其它關鍵技術製程整合研究及應力量測熱傳導模型分析( III ) 2012
5 三維積體電路(3D IC)之矽晶直通孔(TSV)與其它關鍵技術製程整合研究及應力量測熱傳導模型分析( II ) 2011
6 三維積體電路(3D IC)關鍵技術之研究
 2010
7 三維積體電路(3D IC)之矽晶直通孔(TSV)與其它關鍵技術製程整合研究及應力量測熱傳導模型分析(I)
 2010
8 三維積體電路(3D IC)關鍵技術之研究
 2009

Proceedings Paper

序號
No.		 標題
Title		 著作日期
Date
1 Co-sputtered Cu/Ti Bonded Interconnects for 3D Integration Applications 2013-01-01
2 Low Temperature (< 180 degrees C) Bonding for 3D Integration 2013-01-01
3 Near-/Sub-V-th Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection 2013-01-01
4 Electrical Investigation and Reliability of 3D Integration Platform using Cu TSVs and Micro-Bumps with Cu/Sn-BCB Hybrid Bonding 2013-01-01
5 TSV-Based Quartz Crystal Resonator Using 3D Integration and Si Packaging Technologies 2013-01-01
6 Low Temperature (< 180 degrees C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration 2013-01-01
7 Multi-Layer Adaptive Power Management Architecture for TSV 3DIC Applications 2013-01-01
8 Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications 2013-01-01
9 Electrical Performances and Quality Investigations of Integrated Bonded Structures and TSVs for 3D Interconnects 2012-01-01
10 Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration 2012-01-01
11 Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations 2012-01-01
12 Investigation and Effects of Wafer Bow in 3D Integration Bonding Schemes
 2010-12-01

Thesis

序號
No.		 標題
Title		 著作日期
Date
1 三維積體電路技術之銅/銦金屬低溫接合面研究 2014
2 Investigation of Low-Temperature Wafer Bonding and Its Applications for 3D Integration 2014
3 三維積體電路關鍵技術 於先進背照式感光元件應用之研究
 2013
4 包含暫時接合及自底向上矽穿孔成型之前瞻三維積體電路製程整合及技術研究 2013
5 三維異質整合技術之低溫混合接合於發光二極 體元件應用 2013
6 共鍍銅鈦金屬在三維接合連線之電性分析及可靠度測量
 2012
7 三維積體電路之銅/鈦接合及其應用之研究 2012
8 附著力強度與異質接合於三維積體電路應用之研究
 2012
9 三維積體電路關鍵技術之矽穿孔導線研究 2012
10 超薄化矽轉移與氧化矽接合在背照式感光元件上之應用
 2012
11 三維積體電路技術之銅/銦金屬低溫接合研究 2012
12 三維積體電路之銅/銦/錫低溫接合及可靠度研究 2012
13 利用調適性集合組態架構減少單晶片多處理器變相化末級快取之衝突失誤 2011
14 三維積體電路關鍵技術之金屬高分子混合接合研究 2011
電機學院