Browsing by Author "Altolaguirre, Federico A."

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Active ESD Protection for Input Transistors in a 40-nm CMOS Process
(2015)
Altolaguirre, Federico A.
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a novel design for input ESD protection. By replacing the protection resistor with an active switch that isolates the input transistors from the pad under ESD stress, the ESD robustness can be greatly improved. The proposed designs were designed and verified in a 40-nm CMOS process using only thin oxide devices, which can successfully pass the typical industry ESD-protection specifications of 2-kV HBM and 200-V MM ESD tests.
Area-Efficient ESD Clamp Circuit With a Capacitance-Boosting Technique to Minimize Standby Leakage Current
(2015-06-01)
Altolaguirre, Federico A.
;
Ker, Ming-Dou
;
光電學院
;
電子工程學系及電子研究所
;
College of Photonics
This paper presents a new RC-based power-rail electrostatic discharge (ESD) clamp circuit, which achieves ultra-low leakage current while maintaining low silicon utilization. A capacitance-boosting technique is used in conjunction with mathematical analysis of area utilization to determine the best set of parameters to achieve the smallest implementation area in silicon. The proposed power-rail ESD clamp circuit has been verified in a 65-nm general-purpose CMOS process, which achieves an ultra-low standby leakage current of 80 nA at 25 degrees C under 1-V bias, as well as ESD robustness of a 4-kV human body model and a 250-V machine model with a silicon area of only 45 mu m x 17 mu m.
Low-Leakage Bidirectional SCR With Symmetrical Trigger Circuit for ESD Protection in 40-nm CMOS Process
(2016-12)
Altolaguirre, Federico A.
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel bidirectional electrostatic discharge protection device based on a dual silicon-controlled rectifier with a symmetrical trigger circuit. The proposed device has been realized and verified in a 40-nm CMOS process, which can pass a 3.75-kV HBMand a 250-VMM with a very low standby leakage current of similar to 27 nA at 25 degrees C and a bias voltage of 0.9 V with a silicon footprint of only 13 mu m x 100 mu m.
Power-Rail ESD Clamp Circuit with Embedded-Trigger SCR Device in a 65-nm CMOS Process
(2014-01-01)
Altolaguirre, Federico A.
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
SCR is the preferred ESD protection device in nanoscale CMOS technologies due to the better area efficiency compared the BIGFET, virtually no leakage current and smaller capacitance. The main drawback of the SCR is the slow turn-on speed, which is solved by adding dummy gates to block the STI formations inside the SCR structure. This work demonstrates that the dummy gate inside the SCR can be effectively used as an embedded trigger transistor, eliminating the need of an external trigger transistor in the ESD protection circuit and so further reducing silicon area and standby leakage current.
Quad-SCR Device for Cross-Domain ESD Protection
(2016-08)
Altolaguirre, Federico A.
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new electrostatic discharge (ESD) protection device, called quad-silicon controlled rectifier (QSCR), is proposed and verified in a 0.25-mu m CMOS process. The QSCR is designed to be used as ESD protection between separated power domains. Since the QSCR embeds four SCRs between its four terminals, no extra ESD clamps are needed to protect the interface circuits between two separated power domains. Implementations with different circuit topologies were also analyzed to achieve a comprehensive ESD protection design for different applications. From the experimental results, the QSCR can withstand 8-kV HBM and 600-V MM ESD stresses with a silicon area of 75 mu m x 100 mu m.
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
(2013-01-01)
Altolaguirre, Federico A.
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25 degrees C, and a ESD robustness of 3kV HBM and 200V MM.
Ultra-Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm CMOS Technology
(2013)
Altolaguirre, Federico A.
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The gate tunneling current impacts seriously on the power-rail ESD clamp circuit, causing a large leakage current through the MOS capacitor used in ESD detection. In this work, a novel technique is implemented to eliminate the gate leakage current through the MOS capacitor by using a couple of transistors to control the voltage drop across the RC delay in the ESD detection circuit. This circuit has been verified in a 65-nm CMOS technology, with a total leakage current of 165nA under 1V bias, at 25 degrees C, and a ESD robustness of 3kV HBM and 200V MM.