Browsing by Author "CHEN, LJ"
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Item type:Item, A COMPREHENSIVE STUDY OF SUPPRESSION OF BORON PENETRATION BY AMORPHOUS-SI GATE IN P+-GATE PMOS DEVICES(1995-12-01) ;LIN, CY ;JUAN, KC ;CHANG, CY ;PAN, FMCHOU, PFThis paper presents a comprehensive study of the impact of the silicon gate structure on the suppression of boron penetration in p(+)-gate devices, The characteristics and reliability for different gate structures (poly-Si, alpha-Si, poly-Si/poly-Si, poly-Si/alpha-Si, alpha-Si/poly-Si, and alpha-Si/alpha-Si) in p(+) polygate PMOS devices are investigated in detail, The suppression of boron penetration by the nitrided gate oxide is also discussed, The comparison is based on flatband voltage shift as well as the value of charge to breakdown. Results show that the effect of boron diffusion through the thin gate oxide in p(+) polygate PMOS devices can be significantly suppressed by employing the as-deposited amorphous silicon gate, Stacked structures can also be employed to suppress boron penetration at the expense of higher polygate resistance, The single layer as-deposited amorphous silicon is a suitable silicon gate material in the p(+)-gate PMOS device for future dual-gate CMOS process, In addition, by employing a long time annealing at 600 degrees C prior to p(+)-gate ion implantation and activation, further improvements in suppression of boron penetration, polygate resistance, and gate oxide reliability can be achieved for the as-deposited amorphous-Si gate, Modifying the silicon gate structure instead of the gate dielectrics is an effective approach to suppress the boron penetration effect.Item type:Item, CROSS-SECTIONAL TRANSMISSION ELECTRON-MICROSCOPE STUDY OF THE GROWTH-KINETICS OF HEXAGONAL MOSI2 ON (001)SI(1987-03-15) ;CHENG, JY ;CHENG, HC ;CHEN, LJ ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsItem type:Item, DIRECT OBSERVATION OF SI DELTA-DOPED GAAS BY TRANSMISSION ELECTRON-MICROSCOPY(1992-05-25) ;LIU, DG ;FAN, JC ;LEE, CP ;TSAI, CMCHANG, KHDirect observation of the Si delta-doped layer in GaAs has been achieved by high resolution transmission electron microscopy. Samples with different Si doses, from half a monolayer to two monolayers, were studied. The observed spreading of the delta-doped layer showed that Si atoms are largely confined in five monolayers at most (in the highest dose case), indicating excellent confinements of dopants in GaAs. From the images, the Si atoms were uniformly distributed in the doped layer, no cluster formation was observed. For delta-doped GaAs grown at low temperature (480-degrees-C), stacking faults originated from the doped layers were observed. These faults were thought to be caused by the large unrelaxed strain in the low-temperature grown GaAs.Item type:Item, ELECTRICAL AND MICROSTRUCTURAL CHARACTERISTICS OF TI CONTACTS ON (001)SI(1993-08-15) ;LIAUH, HR ;CHEN, MC ;CHEN, JF ;CHEN, LJ電子工程學系及電子研究所An investigation of the electrical and microstructural characteristics of the Ti contact on silicon has been carried out. The presence of As in Ti/n+-Si samples was found to retard the formation of polycrystalline silicide (p-silicide) compared with that in Ti/p+-Si samples with BF2+ implantation. Amorphous interlayers (a-interlayers) were found to be present in both Ti/n-Si and Ti/p-Si samples annealed at temperatures of and lower than 450-degrees-C. Although the Schottky barrier heights (SBH's) vary for about 0.05-0.08 eV for samples annealed over a temperature range from room temperature to 900-degrees-C, SBH's at the a-interlayer/n-Si and a-interlayer/p-Si were measured to be about 0.52-0.54 and 0.59-0.57 eV, respectively. The specific contact resistance (p(c)) in the Ti/n+-Si system was measured to be the lowest with a value of 1.4 X 10(-7) OMEGA cm2 when the a interlayer is present. In Ti/p+-Si system, the minimum rho(c) is about 3 X 10(-7) OMEGA cm2. The variation in contact resistance with annealing temperature for both Ti/n+-Si and Ti/p+-Si samples is correlated to the change in dopant concentration beneath the contacts as well as microstructures. In the temperature regime where the a interlayer is in contact with the silicon substrate, the junction diode leakage current densities (J(leak's)) are considerably lower than those in samples annealed at higher temperatures. The J(leak) at - 6 V reverse bias is lower than 1 nA/cm2. The breakdown voltage is about 14 V (16 V) for the n+/p (p+/n) junction. The thickness of consumed Si is less in samples annealed at low temperature, and the a-interlayer/Si or p-silicide/Si interface is accordingly farther away from the junction as well as the end-of-range defects. The interface of p-silicide/Si is rougher than that of a-interlayer/Si. In addition, the roughness of the p-silicide/Si interface increases with annealing temperature. For both p+/n and n+/p junctions annealed at 900-degrees-C, rough p-silicide/Si interfaces are thought to lead to spiking and increase the leakage currents.Item type:Item, ENHANCEMENT OF OXIDE BREAK-UP BY IMPLANTATION OF FLUORINE IN POLY-SI EMITTER CONTACTED P-+-N SHALLOW JUNCTION FORMATION(1994-04-01) ;WU, SL ;LEE, CL ;LEI, TF ;CHEN, CFCHEN, LJIn this study, it is demonstrated that the incorporation of fluorine can enhance poly-Si/Si interfacial oxide break-up in the poly-Si emitter contacted p+-n shallow junction formation. The annealing temperature for breaking up the poly-Si/Si interfacial oxide has been found to be as low as 900-degrees-C. As a result, the junction depth of the BF2-implanted device is much larger than that of the boron-implanted device.Item type:Item, GROWTH OF SINGLE-CRYSTALLINE COSI2 ON (111) SI IN SOLID-PHASE EPITAXY REGIME BY A NON-ULTRAHIGH VACUUM METHOD(1987-01-26) ;CHENG, HC ;WU, IC ;CHEN, LJ ;電子工程學系及電子研究所Department of Electronics Engineering and Institute of ElectronicsItem type:Item, INFLUENCE OF CONTACT TREATMENTS ON THE ELECTRICAL CHARACTERISTICS OF SHALLOW-JUNCTION TITANIUM-BASED CONTACTS(1992-06-01) ;LIAUH, HR ;TSENG, MF ;CHEN, MC ;CHEN, LJ電子工程學系及電子研究所A comparison of the electrical characteristics of Al-Si/TiW/TiSi2/Si, Al-Si/TiW/Ti/Si and Al-Si/Si contact structures has been carried out. The influence of a contact implantation and anneal on the electrical characteristics of the TiSi2 contacted shallow junctions has also been investigated. Compared with the Al-Si/TiW/TiSi2/Si contact system, the Al-Si/TiW/Ti/Si contact was shown to be a more suitable metalization scheme for the shallow junction contact technology, due to its lower contact resistance and junction leakage as well as its simplicity of fabrication process. The contact resistance of the Ti/n+-Si system was found to be lower than that of the TiSi2/n+-Si system. The low contact resistance of Ti/n+-Si is attributed to the presence of a uniform amorphous interlayer as well as significantly less influence of As on Ti/a-alloy/n+-Si compared to TiSi2/n+-Si. A contact anneal was found to reduce contact resistance for both TiSi2/n+-Si and TiSi2/p+-Si contact systems. With an additional P+ implantation and anneal, the contact resistances are drastically reduced for the n+-Si contacts. On the other hand, a B+ contact implantation and anneal did not significantly improve the contact performance of the TiSi2/p+-S system. The difference is thought to arise from the lower degree of recovery of B+ implantation damage resulted from the contact implantation of TiSi2/p+-Si contact compared to that of TiSi2/n+-Si contact. The addition of the contact P+ implantation increased the total dopant concentration underneath the surface to such an extent that it leads to a reduction in contact resistance.Item type:Item, INTERFACIAL REACTIONS OF TITANIUM THIN-FILMS ON ION-IMPLANTED (001) SI(1993-04-01) ;LIAUH, HR ;CHEN, MC ;CHEN, JF ;CHEN, LJLUR, WAn investigation on the influences of doping impurities on the formation of titanium silicide has been carried out. The formation of polycrystalline silicide was observed to be retarded by the presence of As in Ti/As+-Si samples compared with those in Ti/BF2+-Si samples. Superior thermal stability of TiSi2 was found to occur in BF2+ implanted samples than that in blank and As+ implanted samples. The resistance to island formation in BF2+ implanted samples is attributed to the retardation of grain growth by the segregation of fluorine atoms at the grain boundaries.Item type:Item, INVESTIGATION ON THE DISTRIBUTION OF FLUORINE AND BORON IN POLYCRYSTALLINE SILICON SILICON SYSTEMS(1995-06-01) ;CHEN, TP ;LEI, TF ;CHANG, CY ;HSIEH, WYCHEN, LJThe behaviors of fluorine in BF2+ implanted polycrystalline silicon (poly-Si) on silicon have been investigated in the annealing temperature range of 850 to 1100 degrees C. The distribution of fluorine atoms as functions of temperature and time have been monitored by the secondary ion mass spectroscopy (SIMS) and cross-sectional transmission electron microscopy (XTEM). The XTEM micrographs revealed that fluorine bubbles are distributed in the poly-Si and at the original poly-Si/Si interface after annealing. The locations of bubbles were found to correspond to the fluorine peaks in the SIMS depth-concentration profiles. The presence of the boron peak at the original poly-Si/Si interface is attributed to the gettering of boron atoms by the fluorine bubbles. Moreover, the boron profiles in the silicon substrates are sensitive to thermal budget due to the pileup of fluorine atoms at the poly-Si/Si interface. The pileup of fluorine at the poly-Si/Si interface leads to an enhancement of epitaxial regrowth of poly-Si films and. the formation of fluorine bubbles. Consequently higher surface dopant concentration and deeper junction depth were obtained.Item type:Item, INVESTIGATION ON THE INTERFACE OF THE POLYCRYSTALLINE SILICON CONTACTED DIODE FORMED WITH A STACKED AMORPHOUS-SILICON FILM(1992-08-01) ;WU, SL ;LEE, CL ;LEI, TF ;LEE, TLCHEN, LJThe structural morphology of the poly-single crystalline silicon interface of a diode formed with a stacked-amorphous-silicon (SAS) film has been investigated. Secondary ion mass spectroscopy analyses showed the existence of multi-dopant segregation peaks at each layer boundary and at the poly-single crystalline silicon interface. The break-up at the poly-single silicon interface and the epitaxial regrowth of the polysilicon realigned to the silicon substrate were found to depend not only on the polysilicon deposition and the post annealing conditions, but also on the number and the thickness of the stacked amorphous silicon layers. For the diode formed with a six-layer stacked amorphous silicon, break-up of the interface was found to occur even at an annealing temperature as low as 900-degrees-C. After an additional annealing at 1000-degrees-C for 20 min, the interface was fully broken-up and the epitaxial regrowth layer of the polysilicon could be as thick as 760 angstrom.Item type:Item, LOW-TEMPERATURE GROWTH OF SILICON-BORON LAYER BY ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION(1994-04-04) ;CHEN, TP ;LEI, TF ;LIN, HC ;CHANG, CYHSIEH, WYA polycrystalline silicon-boron (Si-B) layer with a thickness of 180 nm was grown on recrystallized amorphous silicon in an ultrahigh vacuum chemical vapor deposition (UHV/CVD) system using pure SiH4 and B2H6 (1% in H-2). The growth temperature was as low as 550-degrees-C. Auger electron spectroscopy and secondary ion mass spectroscopy showed that the boron concentration is extraordinarily high (2 x 10(22) cm-3). From the analysis of transmission electron diffraction patterns, the phase of silicon hexaboride (SiB6) was found to be present in the as-deposited Si-B layer. After thermal annealing, most of the boron atoms in the Si-B layer were found to be immobile. The presence of SiB6 in the Si-B layer may lead to the reduction of boron diffusivity in the Si-B layer during thermal annealing.Item type:Item, NANOMETER THICK SI/SIGE STRAINED-LAYER SUPERLATTICES GROWN BY AN ULTRAHIGH-VACUUM CHEMICAL-VAPOR-DEPOSITION TECHNIQUE(1994-04-01) ;CHANG, TC ;CHANG, CY ;JUNG, TG ;TSAI, WCWANG, PJHigh quality Si/Si1-xGex superlattices having layers as thin as 1.5 nm have been grown by an ultrahigh vacuum/chemical vapor deposition system. High-resolution double-crystal x-ray diffraction, and conventional and high-resolution cross-sectional transmission electron microscopy were used to evaluate the crystalline quality of these superlattices. A dynamical x-ray simulation program was employed to analyze the experimental rocking curves. Excellent matches between experimental rocking curves and simulated ones were obtained for all superlattices with various periodicity. A cross-sectional transmission electron micrograph of an 80 period Si(4.2 nm)/Si0.878Ge0.122 (1.5 nm) superlattice, in which each individual layers was clearly resolved, demonstrated the capability of this growth technique for nanometer thick layer deposition.Item type:Item, PRECISE DETERMINATION OF ALUMINUM CONTENT IN ALGAAS(1991-11-01) ;CHANG, KH ;LEE, CP ;WU, JS ;LIU, DGLIOU, DCThe Al composition of AlGaAs has been determined by four methods: high-resolution transmission electron microscopy (HRTEM), reflection high-energy electron diffraction (RHEED), photoluminescence (PL), and double-crystal x-ray diffraction (DCXRD). HRTEM is direct and the most accurate method because it does not involve any formula or extrapolation. Using the result obtained from HRTEM as a standard, we have calibrated the results from other methods. RHEED intensity oscillation is found to be accurate and reliable, if the growth conditions are correctly chosen. Comparing the PL results with those determined from HRTEM and RHEED, we suggest three formulas to determine the Al contents at different temperatures. We also proposed a polynomial to determine the Al concentration using the DCXRD measurement.Item type:Item, SCHOTTKY-BARRIER HEIGHTS OF THE AMORPHOUS INTERLAYER SI INTERFACES IN TITANIUM THIN-FILMS ON (001)SI(1992-11-02) ;LIAUH, HR ;CHEN, MC ;CHEN, JF ;CHEN, LJ電子工程學系及電子研究所Schottky barrier heights (SBHs) of amorphous interlayer/Si interfaces in Ti thin films on (001)Si have been measured by forward current-voltage technique. A-interlayers were observed to form by cross-sectional transmission electron microscopy in both Ti thin films on n- and p-type silicon systems in samples annealed at temperatures of and lower than 450-degrees-C for 30 s. Although the SBHs vary for about 0.05-0.08 eV for samples annealed over a temperature range from room temperature to 900-degrees-C, SBHs at the a-interlayer/n-Si and a-interlayer/p-Si were measured to be 0.52-0.54 and 0.59-0.57 eV, respectively. Formation of homogeneous metal a-interlayer/Si interfaces correlated with their SBHs in a number of refractory metal-silicon systems promises to greatly clarify the SBH formation mechanisms.Item type:Item, SIMULTANEOUS OCCURRENCE OF MULTIPHASES IN THE INTERFACIAL REACTIONS OF ULTRAHIGH-VACUUM DEPOSITED HF AND CR THIN-FILMS ON (111)SI(1993-03-08) ;HSIEH, WY ;LIN, JH ;CHEN, LJ ;交大名義發表材料科學與工程學系Simultaneous occurrence of multiphases were observed in the interfacial reactions of ultrahigh vacuum deposited Hf and Cr thin films on (111) Si by high-resolution transmission electron microscopy in conjunction with fast Fourier transform diffraction analysis and image simulation. For Hf/Si system, an amorphous interlayer, Hf5Si3 as well as FeB and CrB types of HfSi were found to form simultaneously in samples annealed at 530-degrees-C for 40-80 min. For Cr/Si system, an amorphous interlayer, Cr5Si3, CrSi, and CrSi2 were observed to form in samples annealed at 375-degrees-C for 30 min. The formation of multiphases appeared to be quite general in the initial stages of interfacial reactions of ultrahigh vacuum deposited refractory thin films. The results called for a reexamination of generally accepted ''difference'' in reaction sequence between bulk and thin-film couples.Item type:Item, SUPPRESSION OF THE BORON PENETRATION INDUCED SI/SIO2 INTERFACE DEGRADATION BY USING A STACKED-AMORPHOUS-SILICON FILM AS THE GATE STRUCTURE FOR PMOSFET(1994-05-01) ;WU, SL ;LEE, CL ;LEI, TF ;CHEN, JFCHEN, LJThis letter reports that the boron penetration through the thin gate oxide into the Si substrate does not only cause a large threshold voltage shift but also induces a large degradation in the Si/SiO2 interface. An atomically flat Si/SiO2 interface can be easily obtained by using a stacked-amorphous-silicon (SAS) film as the gate structure for p+ poly-Si gate MOS devices even the annealing temperature is as high as 1000-degrees-C.