Browsing by Author "Chang, Chia-Wen"

Now showing 1 - 20 of 20

A Near-Threshold Cell-Based All-Digital PLL with Hierarchical Band-Selection G-DCO for Fast Lock-In and Low-Power Applications
(2015-08-01)
Chang, Chia-Wen
;
Chu, Yuan-Hua
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a cell-based all-digital phase-locked loop (ADPLL) with hierarchical gated digitally controlled oscillator (G-DCO) for low voltage operation, wide frequency range as well as low-power consumption. In addition, a new time-domain hierarchical frequency estimation algorithm (HFEA) for frequency acquisition is proposed to estimate the output frequency in 1.5M(F) (M-F = 3 in this paper) cycles and this fast lock-in time is suitable to the dynamic voltage frequency scaling (DVFS) systems. A hierarchical G-DCO is proposed to work at low supply voltage to reduce the power consumption and at the same time to achieve wide frequency range and precise frequency resolution. The core area of the proposed ADPLL is 0.02635 mm(2). In near-threshold region (V-DD = 0.36 V), the proposed ADPLL only dissipates 68.2 mu W and has a rms period jitter of 1.25% UI at 60 MHz output clock frequency. Under 0.5 V V-DD operation, the proposed ADPLL dissipates 404.2 mu W at 400 MHz. The fast lock-in time of 4.489 mu s and the low jitter performance below 0.5% UI at 400 MHz output clock frequency in the proposed ADPLL are suitable in event-driven or DVFS applications.
A simple Spacer technique to fabricate poly-Si TFTs with 50-nm nanowire channels
(2007-11-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Chang, Hong-Ren
;
Chang, Che-Lun
;
Lei, Tan-Fu
In this letter, polycrystalline-silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels, which are fabricated without advanced photolithography by using a side-wall spacer-formation technique, are proposed for the first time. Because the polygate electrode is perpendicularly across poly-Si NW channels to form a trigatelike structure, the proposed poly-Si NW TFT owns outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.
A Varactor-Based All-Digital Multi-Phase PLL with Random-Sampling Spur Suppression Techniques
(2016-04-01)
Chang, Chia-Wen
;
Lo, Kai-Yu
;
Ibrahim, Hossameldin A.
;
Su, Ming-Chiuan
;
Chu, Yuan-Hua
This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm(2)). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V-DD = 0.52 V), the ADPLL only dissipates 269.9 mu W at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of 57.3 dBc with the period jitter of 0.217% UI.
Applying jump-diffusion processes to liquidate and convert venture capital
(2010-08-01)
Lin, Tyrone T.
;
Ko, Chuan-Chuan
;
Chang, Chia-Wen
;
經營管理研究所
;
Institute of Business and Management
This study attempts to apply real options and expand the model designed by Lin and Huang [Lin, T.T., Huang, Y.T.: J. Technol. Manage. 8(3), 59-78 (2003)], which helps venture capital (VC) companies to optimize project exit decisions. The expected discounted factor and a jump-diffusion process combine to assess the value of a start-up company, and determine the threshold of the exit timing of liquidation or convertibility for establishing the optimal disinvestment evaluation model for VC companies. When the project value is below V(L)*, the VC company carries out liquidation, but when the project value exceeds V(C)*, the VC company performs convertibility. The project value is ranging between (V(L)*, V(C)*), and the best choice is holding the decision and waiting to carry out the rights of liquidation and convertibility next time. Besides, this work attempts to identify the expected discounted time in terms of the investment time for VC companies.
Applying jump-diffusion processes to liquidate and convert venture capital
(2010-08-01)
Lin, Tyrone T.
;
Ko, Chuan-Chuan
;
Chang, Chia-Wen
;
經營管理研究所
;
Institute of Business and Management
This study attempts to apply real options and expand the model designed by Lin and Huang [Lin, T.T., Huang, Y.T.: J. Technol. Manage. 8(3), 59-78 (2003)], which helps venture capital (VC) companies to optimize project exit decisions. The expected discounted factor and a jump-diffusion process combine to assess the value of a start-up company, and determine the threshold of the exit timing of liquidation or convertibility for establishing the optimal disinvestment evaluation model for VC companies. When the project value is below V(L)*, the VC company carries out liquidation, but when the project value exceeds V(C)*, the VC company performs convertibility. The project value is ranging between (V(L)*, V(C)*), and the best choice is holding the decision and waiting to carry out the rights of liquidation and convertibility next time. Besides, this work attempts to identify the expected discounted time in terms of the investment time for VC companies.
CF4-plasma-induced fluorine passivation effects on poly-Si TFTs with high-kappa Pr2O3 gate dielectric
(2008)
Chang, Chia-Wen
;
Huang, Po-Wei
;
Deng, Chih-Kang
;
Huang, Jiun-Jia
;
Chang, Hong-Ren
High-performance polycrystalline silicon thin-film transistors (poly-Si TFTs) integrating high-kappa Pr2O3 gate dielectric and fluorine-passivated poly-Si film are demonstrated. High gate capacitance density and thin equivalent-oxide thickness provided by the high-kappa Pr2O3 gate dielectric have the advantage of increasing the driving current capability of the TFT device, but an undesirable off-state leakage current could be introduced from the high electric field near the drain side. Introducing fluorine atoms into poly-Si films by employing a low-temperature CF4 plasma treatment can effectively passivate the trap states. With 10 W CF4 plasma treatment on poly-Si film, the electrical characteristics of poly-Si Pr2O3 TFTs can be significantly improved, including a steeper subthreshold swing, smaller threshold voltage, higher field-effect mobility, and better on/off current ratio compared with that without CF4 plasma treatment. The maximum off-state leakage current of the fluorine-passivated TFT is more than one order of magnitude lower than that of the control TFT. Furthermore, the incorporation of fluorine atoms by CF4 plasma treatment also improves the reliability of poly-Si Pr2O3 TFTs against hot carrier stressing, which is due to the formation of stronger Si-F bonds in place of weak Si-H bonds in the poly-Si channel and at the Pr2O3 gate dielectric/poly-Si interface. Therefore, high-performance and high-reliability poly-Si TFTs with Pr2O3 gate dielectric and CF4 plasma treatment on poly-Si film are suitable for active-matrix liquid crystal display application. (c) 2007 The Electrochemical Society.
Characteristics of Pr2O3 gate dielectric thin-film transistors fabricated on fluorine-ion-implanted polysilicon films
(2007)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Huang, Jiun-Jia
;
Chang, Hong-Ren
;
Lei, Tan-Fu
A simple and effective scheme for fabricating high dielectric constant (high-kappa) praseodymium oxide (Pr2O3) gate dielectric thin-film transistors (Pr2O3 TFT) on fluorine-ion-implanted polysilicon films was proposed and demonstrated for the first time. Incorporating the fluorine-incorporation method with high-kappa Pr2O3 gate dielectric cannot only effectively passivate the trap states in the poly-Si film but also significantly increase the gate capacitance density. With the incorporation of fluorine ions, the electrical characteristics of Pr2O3 TFT can be remarkably improved, including smaller threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower gate-induced drain leakage current, and better on/off current ratio. In addition, the incorporation of fluorine ions in the poly-Si film also improves the reliability of Pr2O3 TFT against hot-carrier stress, which is attributed to the formation of stronger Si-F bonds. Therefore, the proposed scheme is a promising technology for high-performance solid-phase crystallized poly-Si TFTs. (c) 2007 The Electrochemical Society. All rights reserved.
Characterizing fluorine-ion implant effects on poly-Si thin-film transistors with Pr2O3 gate dielectric
(2008-06-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Wu, Shih-Chieh
;
Huang, Jiun-Jia
;
Chang, Hong-Ren
The fluorine ion implantation applied to the polycrystalline silicon thin-film transistors (poly-Si TFTs) with high-k. Pr2O3 as gate dielectric is investigated for the first time. Using the Pr2O3 gate dielectric can obtain a high gate capacitance density and thin equivalent-oxide thickness, exhibiting a greatly enhancement in the driving capability of TFT device. Introducing fluorine ions into the poly-Si film by fluorine ion implantation technique can effectively passivate the trap states in the poly-Si film and at the Pr2O3/poly-Si interface to improve the device electrical properties. The Pr2O3 TFTs fabricated on fluorine-implanted poly-Si film exhibit significantly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, higher field-effect mobility, lower off-state leakage current, and higher on/off current ratio, as compared with the control poly-Si Pr2O3 TFTs. Also, the incorporation of fluorine ions also improves the reliability of poly-Si Pr2O3 TFTs against hot-carrier stressing, which is attributed to the formation of stronger Si-F bonds. Furthermore, superior threshold-voltage rolloff characteristic is also demonstrated in the fluorine-implanted poly-Si Pr2O3 TFTs. Therefore, the proposed scheme is a promising technology for high-performance and high-reliability solid-phase crystallized poly-Si TFT.
Electrical enhancement of poly-Si TFTs using FSG ILD passivation
(2007)
Huang, Jiun-Jia
;
Chang, Chia-Wen
;
Dneg, Chih-Kang
;
Lei, Tan-Fu
;
電子工程學系及電子研究所
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with fluorinated silicate glass (FSG) inter-layer dielectric (ILD) passivation layer were proposed in this study. The outdiffused fluorine atoms from FSG ILD could replace Si dangling bonds at grain boundaries in poly-Si film. The proposed short-channel poly-Si TFTs with FSG ILD passivation have electrical enhancement, including on current, off current, and kink effect, compared to those with undoped SiO2 ILD passivation.
Electrical enhancement of polycrystalline silicon thin-film transistors using fluorinated silicate glass passivation layer
(2008-02-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Huang, Jiun-Jia
;
Wang, Tong-Yi
;
Lei, Tan-Fu
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with a fluorinated silicate glass (FSG) passivation layer are proposed and demonstrated in this study. Experimental results reveal that the electrical characteristics can be improved by the incorporation of appropriate amounts of fluorine in the poly-Si film. The poly-Si TFTs with a FSG passivation layer show a high on-current, a low off-state gate-induced drain leakage (GIDL) current, a high field-effect mobility, and a suppressed kink effect, compared with the poly-Si TFTs with an undoped SiO(2) passivation layer. The presence of incorporated fluorine atoms from the FSG passivation layer in the poly-Si channel film can passivate the trap states at the grain boundaries. Furthermore, the incorporation of fluorine atoms can form stronger Si-F bonds near the source and drain sides to enhance the immunity against hot-carrier stress. In addition, the proposed poly-Si TFTs are easy to fabricate, have a low production cost, and are realized using a process compatible with modern TFT manufacturing technology.
Enhanced performance and reliability for solid phase crystallized poly-Si TFTs with argon ion implantation
(2007)
Chang, Chia-Wen
;
Chang, Che-Lun
;
Luo, Wun-Chen
;
Lee, Jam-Wem
;
Lei, Tan-Fu
Performance and reliability improvement for polycrystalline silicon thin-film transistors (poly-Si TFrs) with Argon ion implantation are proposed for the first time. By adopting this novel surface -nucleation solid -phase-cry stallization scheme, not only the grain size of poly-Si can be increased but also the intragranular defects can be suppressed effectively. Therefore, a high quality of poly-Si film in channel with better crystallinity is formed. Argon-implanted TFrs have been successfully fabricated and the experimental results demonstrate a superior field-effect mobility of 46. 06 cm(2)/VS, a fewer grain boundary trap density of 3.44 x 10(12) cm(-2) than those of conventional TFrs. The novel proposed structure is a very promising candidate for the future high-performance large-area device applications.
Enhanced performance and reliability for solid-phase crystallized poly-Si TFTs with argon ion implantation
(2007-01-01)
Chang, Chia-Wen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
High-performance solid-phase crystallized (SPC) polycrystalline silicon thin-film transistors (TFTs) with argon ion implantation (argon-implanted poly-Si TFTs) are proposed in this study. Compared to the control poly-Si TFT, the argon-implanted poly-Si TFT has superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, steeper subthreshold swing, lower trap state density, etc. These electrical performance improvements could be attributed to the fine microstructure of the SPC poly-Si film improved by deep argon ion implantation beyond the interface of amorphous Si and underlying oxide. Therefore, a high-quality poly-Si channel accompanied with larger grain size and lower grain boundary trap states could be obtained. Moreover, the argon-implanted poly-Si TFT also exhibits an improved hot-carrier stress immunity owing to reduced weak Si-Si or Si-H bonds from fewer grain boundaries in the poly-Si channel. (c) 2007 The Electrochemical Society.
Enhanced performance and reliability for solid-phase crystallized poly-Si TFTs with argon ion implantation (vol 154, pg J375, 2007)
(2008)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Chang, Che-Lun
;
Lei, Tan-Fu
;
電子工程學系及電子研究所
High-performance nanowire TFTs with metal-induced lateral crystallized poly-Si channels
(2008-05-01)
Chang, Chia-Wen
;
Chen, Szu-Fen
;
Chang, Che-Lun
;
Deng, Chih-Kang
;
Huang, Jiun-Jia
High-performance poly-Si thin-film transistors (TFTs) with 50-nm nanowire (NW) channels fabricated by integrating a simple spacer formation scheme and metal-induced-lateral-crystallization (MILC) technique are proposed. By using the sidewall spacer formation scheme, the NW channels with nanometer-scale feature sizes can be easily fabricated, exhibiting superior channel controllability through the triple-gate structure. In employing the MILC technique, the grain crystallinity of NW channels is significantly superior to that formed by the solid-phase-crystallization (SPC) technique. Therefore, the MILC NW TFT exhibits greatly improved electrical performances, including lower threshold voltage, steeper subthreshold swing, and higher field-effect mobility, as compared to those of the SPC NW TFT. Moreover, the superior threshold-voltage rolloff characteristics of MILC NW TFT are also demonstrated.
High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with floating-channel structure
(2008-04-01)
Chang, Chia-Wen
;
Deng, Chih-Kang
;
Chang, Che-Lun
;
Liao, Ta-Chuan
;
Lei, Tan-Fu
High-performance solid-phase crystallized polycrystalline silicon thin-film transistors with a floating-channel active region (FC poly-Si TFTs) are proposed in this study. A high-quality poly-Si channel film accompanied by a larger grain size and fewer microstructural defects could be obtained. Compared with the conventional poly-Si TFTs (CN poly-Si TFTs), the fabricated FC poly-Si TFTs exhibit superior electrical characteristics, including lower threshold voltage, higher field-effect mobility, and lower trap state density. These electrical performance improvements could be attributed to the fact that the a-Si film with a floating-channel structure can relieve the stress generated from the crystallization process accompanying the trap state density reduction and grain size enhancement. In addition, the FC poly-Si TFTs also exhibit improved hot-carrier stress immunity due to the reduced weak Si-H bonds from fewer grain boundaries in the poly-Si channel. Therefore, the proposed FC poly-Si TFTs can be easily fabricated by conventional solid-phase crystallization, and suitable for future high-performance flat-panel display applications.
Improvement of electrical characteristics for fluorine-ion implanted poly-Si TFTs using Pr2O3 gate dielectric
(2007)
Chang, Chia-Wen
;
Huang, Jiun-Jia
;
Chang, Hong-Ren
;
Lei, Tan-Fu
;
電子工程學系及電子研究所
High-performance fluorine-ion-implanted poly-Si thin-film transistors with high-k Pr2O3 gate dielectric are demonstrated for the first time. Experimental results have shown that the fluorine-doped poly-Si channel would effectively minimize the trap state densities, leading to improved electrical characteristics even without any hydrogenation process or advanced crystallization techniques. In addition, the presence of fluorine in poly-Si TFT obviously exhibits superior electrical reliability. This unique low cost, and effective fluorine ion implantation technique makes the Pr2O3 gate dielectric TFT very suitable for low power peripheral driving circuit applications.
Improvement of electrical characteristics for novel process-compatible floating channel solid-phase crystallized poly-Si TFTs
(2007)
Chang, Chia-Wen
;
Chang, Che-Lun
;
Lee, Jam-Wem
;
Lei, Tan-Fu
;
電子工程學系及電子研究所
High-performance polycrystalline-silicon thin-film transistors (poly-Si TFTs) with floating channel solid-phase crystallization are proposed for the first time. By adopting this novel crystallization scheme, a better crystalline poly-Si film can be obtained in the suspended channel film. Poly-Si TFTs with this novel floating channel structure have been successfully fabricated and the experimental results demonstrate a superior electrical performance and reliability.
Performance and reliability improvement for poly-Si TFTs using fluorinated silicate glass inter-layer-dielectric passivation
(2007)
Chang, Chia-Wen
;
Wu, Tin-Wei
;
Wang, Tong-Yi
;
Chang, Che-Lun
;
Lee, Jam-Wem
Polycrystalline silicon thin-film transistors (poly-Si TFTs) with fluorinated silicate glass (FSG) inter-layer dielectric (ILD) passivation layer were proposed and demonstrated in this study. The presence of outdiffused fluorine atoms from FSG layer can eliminate Si dangling bonds at the grain boundaries near the drain side. The proposed short channel poly-Si TFTs with FSG ILD passivation have a slightly improved on-current, a obviously suppressed serious kink-effect, and a remarkably reduced off-leakage current than those with undoped SiO2 ILD passivation. Furthermore, the incorporation of fluorine atoms in poly-Si film can also form stronger Si-F bonds at drain side to enhance the immunity to hot carrier stress. Besides, the proposed TFTs structure is simple, low cost, and process compatible with present TFTs manufacturing technology.
Spacer technique to fabricate pSi TFTs with 50nm nanowire channels
(2008)
Chang, Chia-Wen
;
Chen, Szu-Fen
;
Wu, Shih-Chieh
;
Lin, Guan-Liang
;
Lei, Tan-Fu
In this work, polycrystalline silicon thin-film transistors (poly-Si TFTs) with 50-nm nanowire (NW) channels fabricated without advanced photolithograph v I v using a sidewall spacer formation technique are proposed for the first time. Because the poly gate electrode is perpendicularly across poly-Si NW channels to form a tri-gate-like structure, the proposed poly-Si NW TFT owns an outstanding gate controllability. In summary, a simple and low-cost scheme is proposed to fabricate high-performance poly-Si NW TFT suitable for future display manufacturing and practical applications.
Synthesizable Injection-Locked Phase-Locked Loop with Multiphase Interlocking Digitally Controlled Oscillator Arrays
(2019-01-01)
Su, Yu-Cheng
;
Chang, Kang-Yu
;
Chin, Yu-Tung
;
Chang, Chia-Wen
;
Jou, Shyh-Jye
A synthesizable injection-locked phase-locked loop with multiphase interlocking digitally controlled oscillator arrays (SILPLL-IDCOs) is proposed. By doing interlocking of two digitally controlled oscillators (DCOs), the number of phase provided can be double and the oscillation frequency can be as fast as the original DCO. Moreover, it also adopts frequency tracking loop to isolate the injection path from the traditional PLL path in the ILPLL, so the race condition in the traditional ILPLL can be resolved. The chip has been designed and implemented in TSMC 40 nm GP 1P10M CMOS process technology. In the proposed synthesizable ILPLL, all logic cells and circuit components are using standard cell provided by foundry and our group. The total area of the synthesizable ILPLL core is only 0.01876 mm(2) and provides 8 phase output. The post-layout simulated RMS jitter from a 5.024 GHz output frequency is 0.048 %UI. The total measured power consumption is 10.97 mW at 5.024 GHz output frequency and 78.5 MHz reference clock.