Browsing by Author "Chang, E. Y."

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60GHz broadband 0/1-level RF-via interconnect for RF-MEMS packaging
(2007-10-25)
Wu, Wc.
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Hsu, L. H.
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Chang, E. Y.
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Starski, J. P.
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Zirath, H.
The RF-via interconnect structure front the 0- to the 1-level package for coplanar RF-MEMS devices packaging is evaluated. The 0/1-level interconnect structure was designed and optimised using the electromagnetic simulation tool. The structure was then successfully fabricated and characterised up to 67 GHz. The measured and simulated results show good agreement, demonstrating DC-to-60 GHz broadband interconnect performance through the two levels package with return loss below 15 dB and insertion loss within 0.6 dB.
Annealing Effect on the Electrical Properties of La2O3/InGaAs MOS Capacitors
(2011-01-01)
Kanda, T.
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Zade, D.
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Lin, Y. -C.
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Kakushima, K.
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Ahmet, P.
The electrical characteristics of InGaAs MOS capacitors with 8-nm-thick La2O3 gate dielectrics have been measured. The effects of annealing temperature and annealing time on the interface state densities (D-it) have been extracted. It has been found that the low Dit can be achieved by lowering the annealing temperature for an extended period of time.
Coaxial transitions for CPW-to-CPW flip chip interconnects
(2007-08-16)
Wu, W. C.
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Chang, E. Y.
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Huang, C. H.
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Hsu, L. H.
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Starski, J. P.
A novel coaxial transition for CPW-to-CPW flip chip interconnect is presented and experimentally demonstrated. To realise the coaxial transition on the CPW circuit, benzocyclobutene was used as the interlayer dielectric between the vertical coaxial transition and the CPW circuit. The coaxial interconnect structure was successfully fabricated and RF characterised to 67 GHz. The structure showed excellent interconnect performance from DC up to 55 GHz with low return loss below 20 dB and low insertion loss less than 0.5 dB even when the underfill was applied to the structure.
Control of metamorphic buffer structure and device performance of InxGa1-xAs epitaxial layers fabricated by metal organic chemical vapor deposition
(2014-12-05)
Nguyen, H. Q.
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Yu, H. W.
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Luc, Q. H.
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Tang, Y. Z.
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Phan, V. T. H.
Using a step-graded (SG) buffer structure via metal-organic chemical vapor deposition, we demonstrate a high suitability of In0.5Ga0.5As epitaxial layers on a GaAs substrate for electronic device application. Taking advantage of the technique\'s precise control, we were able to increase the number of SG layers to achieve a fairly low dislocation density (similar to 10(6)cm(-2)), while keeping each individual SG layer slightly exceeding the critical thickness (similar to 80 nm) for strain relaxation. This met the demanded but contradictory requirements, and even offered excellent scalability by lowering the whole buffer structure down to 2.3 mu m. This scalability overwhelmingly excels the forefront studies. The effects of the SG misfit strain on the crystal quality and surface morphology of In0.5Ga0.5As epitaxial layers were carefully investigated, and were correlated to threading dislocation (TD) blocking mechanisms. From microstructural analyses, TDs can be blocked effectively through self-annihilation reactions, or hindered randomly by misfit dislocation mechanisms. Growth conditions for avoiding phase separation were also explored and identified. The buffer-improved, high-quality In0.5Ga0.5As epitaxial layers enabled a high-performance, metal-oxide-semiconductor capacitor on a GaAs substrate. The devices displayed remarkable capacitance-voltage responses with small frequency dispersion. A promising interface trap density of 3 x 10(12) eV(-1) cm(-2) in a conductance test was also obtained. These electrical performances are competitive to those using lattice-coherent but pricey InGaAs/InP systems.
DC and microwave performance of AlGaN/GaN HEMTs passivated with sputtered SiNx
(2007-07-01)
Shiu, J. Y.
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Desmaris, V.
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Rorsman, N.
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Kumakura, K.
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Makimoto, T.
The effects of sputtered and room temperature plasma enhanced chemical vapour deposition (RT-PECVD) SiNx passivation on the dc and microwave performance of AlGaN/GaN high electron mobility transistors (HEMTs) are studied. The pulsed I - V characteristics from a class B quiescent bias point and transient measurements indicate that the sputtered SiNx passivation is more efficient in suppressing lag effects in AlGaN/GaN HEMTs. Dispersion-free sputtered SiNx passivated AlGaN/GaN HEMTs were obtained using this technique. Continuous-wave (CW) measurements without active cooling give a maximum output power density of 6.6 W mm(-1) at V-gs=- 4 V, V-ds = 50 V and a maximum power added efficiency of 51.3% at V-gs=- 4 V, V-ds = 30 V at 3 GHz on 2 x 50 mu m AlGaN/GaN HEMTs on the sapphire substrate, with a gate length of 2 mu m and without field-plated gates. To the best of our knowledge, this is the highest level power density reported on the sapphire substrate without field-plate design. The extrinsic cut-off frequency (f(t)) and maximum oscillation frequency (f(max)) are 51 GHz and 100 GHz, respectively, on 2 x 50 x 0.15 mu m HEMTs. To our knowledge, the sputtered SiNx passivation for AlGaN/GaN HEMTs is a unique technique, which has never been published before.
Effect of gate sinking on the device performance, of the InGaP/AlGaAs/InGaAs enhancement-mode PHEMT
(2007-02-01)
Chu, L. H.
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Chang, E. Y.
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Chang, L.
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Wu, Y. H.
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Chen, S. H.
An enhancement-mode InGaP/AlGaAs/InGaAs pseudomorphic high-electron mobility transistor using platinum (Pt) as the Schottky contact metal was investigated for the first time. Following the Pt/Ti/Pt/Au gate metal deposition, the devices were thermally annealed at 325 degrees C for gate sinking. After the annealing, the device showed a positive threshold voltage (V-th) shift from 0.17 to 0.41 V and a very low drain leakage current from 1.56 to 0.16 mu A/mm. These improvements are attributed to the Schottky barrier height increase and the decrease of the gate-to-channel distance as Pt sinks into the InGaP Schottky layer during gate-sinking process. The shift in the V-th was very uniform across a 4-in wafer and was reproducible from wafer to wafer. The device also showed excellent RF power performance after the gate-sinking process.
Effect of graded-temperature arsenic prelayer on quality of GaAs on Ge/Si substrates by metalorganic vapor phase epitaxy
(2011-10-24)
Yu, H. W.
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Chang, E. Y.
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Yamamoto, Y.
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Tillack, B.
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Wang, W. C.
The growth of GaAs epitaxy on Ge/Si substrates with an arsenic prelayer grown with graded temperature ramped from 300 to 420 degrees C is investigated. It is demonstrated that the graded-temperature arsenic prelayer grown on a Ge/Si substrate annealed at 650 degrees C not only improves the surface morphology (roughness: 1.1 nm) but also reduces the anti-phase domains' (APDs) density in GaAs epitaxy (dislocation density: similar to 2 x 10(7) cm(-2)). Moreover, the unwanted interdiffusion between Ge and GaAs epitaxy is suppressed by using the graded-temperature arsenic prelayer due to the low energy of the Ge-As bond and the use of a low V/III ratio of 20. (C) 2011 American Institute of Physics. [doi:10.1063/1.3656737]
Effect of substrate misorientation on the material properties of GaAs/Al(0.3)Ga(0.7)As tunnel diodes
(2010-12-06)
Yu, H. W.
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Chang, E. Y.
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Nguyen, H. Q.
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Chang, J. T.
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Chung, C. C.
The effect of substrate misorientation on the material quality of the N(++)-GaAs/P(++)-AlGaAs tunnel diodes (TDs) grown on these substrates is investigated. It is found that the misorientation influences both surface roughness and interface properties of the N(++)-GaAs/P(++)-AlGaAs TDs. Smooth surface (rms roughness: 1.54 angstrom) and sharp interface for the GaAs/Al(0.3)Ga(0.7)As TDs were obtained when the (100) tilted 10 degrees off toward [111] GaAs substrate was used. Besides, the oxygen content in N(++)-GaAs and P(++)-AlGaAs layers grown on the 10 degrees off GaAs substrates was reduced due to the reduction of sticking coefficient and number of anisotropic sites. (C) 2010 American Institute of Physics. [doi:10.1063/1.3525158]
Effect of substrate misorientation on the material properties of GaAs/Al0.3Ga0.7As tunnel diodes
(2010-12-06)
Yu, H. W.
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Chang, E. Y.
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Nguyen, H. Q.
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Chang, J. T.
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Chung, C. C.
The effect of substrate misorientation on the material quality of the N++-GaAs/P++-AlGaAs tunnel diodes (TDs) grown on these substrates is investigated. It is found that the misorientation influences both surface roughness and interface properties of the N++-GaAs/P++-AlGaAs TDs. Smooth surface (rms roughness: 1.54 angstrom) and sharp interface for the GaAs/Al0.3Ga0.7As TDs were obtained when the (100) tilted 10 degrees off toward [111] GaAs substrate was used. Besides, the oxygen content in N++-GaAs and P++-AlGaAs layers grown on the 10 degrees off GaAs substrates was reduced due to the reduction of sticking coefficient and number of anisotropic sites. (C) 2010 American Institute of Physics. [doi:10.1063/1.3525158]
Electrical Characteristics of HfO2 and La2O3 Gate Dielectrics for In0.53Ga0.47As MOS Structure
(2009)
Funamiz, K.
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Lin, Y. C.
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Kakushima, K.
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Ahmet, P.
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Tsutsui, K.
InGaAs MOS capacitors with HfO2 and La2O3 gate dielectrics have been investigated. La2O3 capacitor was found to result in large leakage current. This can be attributed to the annealing-induced As diffusion into La2O3 layer from InGaAs substrate. This leakage current was found to be suppressed by inserting HfO2 layer between La2O3 layer and InGaAs.
Electrical Characterization of Al(2)O(3)/n-InAs Metal-Oxide-Semiconductor Capacitors With Various Surface Treatments
(2011-06-01)
Trinh, H. D.
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Brammertz, G.
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Chang, E. Y.
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Kuo, C. I.
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Lu, C. Y.
Ex situ sulfide and HCl wet chemical treatments in conjunction with in situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al(2)O(3) on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. The capacitance-voltage C-V characterization of Al(2)O(3)/n-InAs structures shows that the frequency dispersion in the accumulation regime is small (< 0.75%/dec) and does not seem to be significantly affected by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the n-channel metal-oxide-semiconductor capacitors. The interface trap density profiles extracted from the simulation mainly show donorlike interface states inside the InAs band gap and in the lower part of the conduction band. The donorlike traps inside the InAs band gap and in the lower part of the conduction band were significantly reduced by using wet-chemical-plus-TMA treatments, in agreement with C-V characteristics.
Electrical Characterization of Al2O3/n-InAs Metal-Oxide-Semiconductor Capacitors With Various Surface Treatments
(2011-06-01)
Trinh, H. D.
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Brammertz, G.
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Chang, E. Y.
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Kuo, C. I.
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Lu, C. Y.
Ex situ sulfide and HCl wet chemical treatments in conjunction with in situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. The capacitance-voltage C-V characterization of Al2O3/n-InAs structures shows that the frequency dispersion in the accumulation regime is small (< 0.75%/dec) and does not seem to be significantly affected by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the n-channel metal-oxide-semiconductor capacitors. The interface trap density profiles extracted from the simulation mainly show donorlike interface states inside the InAs band gap and in the lower part of the conduction band. The donorlike traps inside the InAs band gap and in the lower part of the conduction band were significantly reduced by using wet-chemical-plus-TMA treatments, in agreement with C-V characteristics.
Enhanced lateral heat dissipation packaging structure for GaN HEMTs on Si substrate
(2013-03-01)
Cheng, Stone
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Chou, Po-Chien
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Chieng, Wei-Hua
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Chang, E. Y.
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機械工程學系
This work presents a technology for packaging AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate. The GaN HEMTs are attached to a V-groove copper base and mounted on a TO-3P leadframe. The various thermal paths from the GaN gate junction to the case are carried out for heat dissipation by spreading to protective coating; transferring through the bond wires; spreading in the lateral device structure through the adhesive layer, and vertical heat spreading of silicon chip bottom. Thermal characterization showed a thermal resistance of 13.72 degrees C/W from the device to the TO-3P package. Experimental tests of a 30 mm gate-periphery single chip packaged in a 5 x 3 mm V-groove Cu base with a 100 V drain bias showed power dissipation of 22 W. (c) 2012 Elsevier Ltd. All rights reserved.
Enhancement-Mode GaN MIS-HEMTs with HfLaOx Gate Insulator
(2016)
Lin, Y. C.
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Lin, J. C.
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Lin, Y.
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Wu, C. H.
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Huang, Y. X.
Evaluation of GaN HEMT with Field Plate for Reliability Improvement
(2016)
Lin, Y. C.
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Lin, J. C.
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Lin, Y.
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Wu, C. H.
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Chin, P. C.
Experimental and modeling on atomic layer deposition Al2O3/n-InAs metal-oxide-semiconductor capacitors with various surface treatments
(2011-01-01)
Trinh, H. D.
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Chang, E. Y.
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Brammertz, G.
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Lu, C. Y.
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Nguyen, H. Q.
Ex-situ sulfide and HCl wet chemical treatments in conjunction with in-situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. Capacitance-voltage (C-V) characterization of Al2O3/n-InAs structures shows that the frequency dispersion in accumulation regime is small (<0.75% per decade) and does not seem to be affected significantly by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the nMOS capacitors. The interface trap density profiles extracted from simulation show mainly donor-like interface states inside the InAs bandgap and in the lower part of the conduction band. The donor-like traps inside the InAs bandgap and in the lower part of the conduction band were significantly reduced by using wet chemical plus TMA treatments, in agreement with C-V characteristics.
Experimental and modeling on atomic layer deposition Al2O3/n-InAs metal-oxide-semiconductor capacitors with various surface treatments
(2011-01-01)
Trinh, H. D.
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Chang, E. Y.
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Brammertz, G.
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Lu, C. Y.
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Nguyen, H. Q.
Ex-situ sulfide and HCl wet chemical treatments in conjunction with in-situ trimethyl aluminum (TMA) pretreatment were performed before the deposition of Al2O3 on n-InAs surfaces. X-ray photoelectron spectroscopy analyses show a significant reduction of InAs native oxides after different treatments. Capacitance-voltage (C-V) characterization of Al2O3/n-InAs structures shows that the frequency dispersion in accumulation regime is small (<0.75% per decade) and does not seem to be affected significantly by the different surface treatments, whereas the latter improves depletion and inversion behaviors of the nMOS capacitors. The interface trap density profiles extracted from simulation show mainly donor-like interface states inside the InAs bandgap and in the lower part of the conduction band. The donor-like traps inside the InAs bandgap and in the lower part of the conduction band were significantly reduced by using wet chemical plus TMA treatments, in agreement with C-V characteristics.
First Experimental Demonstration of Negative Capacitance InGaAs MOSFETs With Hf0.5Zr0.5O2 Ferroelectric Gate Stack
(2018-01-01)
Luc, Q. H.
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Fan-Chiang, C. C.
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Huynh, S. H.
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Huang, P.
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Do, H. B.
We demonstrate, for the first time, the negative capacitance (NC) In0.53Ga0.47As nMOSFET with 8-nm Hf0.5Zr0.5O2 (HZO) as ferroelectric (FE) dielectric for sub-60 mV/dec subthreshold swing (SS). The impact of annealing treatments on the FE properties and electrical characteristics of NC InGaAs nMOSFETs are investigated. Optimized annealing condition results in NC effects at the HZO/Al2O3/InGaAs nMOSFETs with steep SS property (similar to 11 mV/dec).
GaN MIS-HEMT with Low Dynamic ON-resistance Using SiON Passivation
(2016-01-01)
Liu, S. C.
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Huang, C. K.
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Chang, E. Y.
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材料科學與工程學系
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電子工程學系及電子研究所
An effective SiON passivation with high density of positive fixed charges for GaN MIS-HEMTs is demonstrated. The positive fixed charges at the SiON/AlGaN interface effectively reduce the surface potential and expand the quantum well below the Fermi level, thus improving the device performance. The GaN MIS-HEMT with SiON demonstrated a high maximum drain-source current density (I-DS,I-max) of > 1 A/mm, a breakdown voltage of 750 V at a drain leakage current of 1 mu A/mm, and a well transfer characteristics. The dynamic ON-resistance only increased slightly under a high quiescent bias of 100 V.
Growth of very-high-mobility AlGaSb/InAs high-electron-mobility transistor structure on si substrate for high speed electronic applications
(2007-01-08)
Lin, Y. C.
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Yamaguchi, H.
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Chang, E. Y.
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Hsieh, Y. C.
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Ueki, M.
The growth of the AlGaSb/InAs high-electron-mobility transistor (HEMT ) epitaxial structure on the Si substrate is investigated. Buffer layers consisted of UHV/chemical vapor deposited grown Ge/GeSi and molecular beam epitaxy-grown AlGaSb/AlSb/GaAs were used to accommodate the strain induced by the large lattice mismatch between the AlGaSb/InAs HEMT structure and the Si substrate. The crystalline quality of the structure grown was examined by x-ray diffraction, transmission electron microscopy, and atomic force microscopy. Finally, very high room-temperature electron mobility of 27 300 cm(2) /V s was achieved. It is demonstrated that a very-high-mobility AlGaSb/InAs HEMT structure on the Si substrate can be achieved with the properly designed buffer layers. (c) 2007 American Institute of Physics.