Browsing by Author "Chen, Che-Wei"

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Body-Tied Germanium FinFETs Directly on a Silicon Substrate
(2012-12-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Luo, Guang-Li
;
Chien, Chao-Hsin
;
電子工程學系及電子研究所
We fabricated body-tied Ge p-channel fin field-effect transistors (p-FinFETs) directly on a Si substrate with a high-kappa/metal gate stack. This scheme is fully compatible with Si standard processing. The FinFET structure has excellent control on the channel potential and thus can improve the short-channel effect. The diode with p(+)-Ge/n-Si heterojunctions illustrates a remarkably high I-ON/I-OFF > 10(6) despite the presence of misfit dislocations at the interface. The high-hole-mobility body-tied Ge p-FinFETs with a fin width W-Fin of similar to 40 nm and a mask channel length L-Mask of 120 nm depict a driving current of 22 mu A/mu m at V-G = -2 V and a low OFF-current of 3 nA/mu m at V-G = 2 V. The subthreshold characteristics with a swing of 228 mV/dec and drain-induced barrier lowering of 288 mV/V are demonstrated.
Body-Tied Germanium Tri-Gate Junctionless PMOSFET With In-Situ Boron Doped Channel
(2014-01-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Tzeng, Ju-Yuan
;
Chang, Pang-Sheng
;
Luo, Guang-Li
In this letter, we demonstrate body-tied Ge tri-gate junctionless (JL) p-channel MOSFETs directly on Si. Our tri-gate JL-PFET exhibits higher current than the conventional inversion-mode transistor through in-situ heavily doped technique and trimming down Ge fin width. We show that the JL-PFET with tri-gate structure has excellent I-ON/I-OFF ratio and good short channel effect control on the channel potential. The current ratio is of similar to 6 x 10(3) (I-D) at V-DS = -0.1 V, V-GS = -3, and 0 V. The relatively low OFF-current is of 6 nA/ mu m at V-DS = -0.1 V and V-GS = 0 V. The subthreshold swing of 203 mV/decade and drain induced barrier lowering of 220 mV/V are reported at L-G = 120 nm.
Combination of Electroencephalography and Near-Infrared Spectroscopy in Evaluation of Mental Concentration during the Mental Focus Task for Wisconsin Card Sorting Test
(2017-03-23)
Chen, Che-Wei
;
Sun, Chia-Wei
;
光電工程學系
;
Department of Photonics
Near-infrared spectroscopy (NIRS) is a noninvasive neuroimaging tool for measuring evoked functional changes in brain oxygenation. Electroencephalography (EEG) can be used to evaluate the functionality of cortical connections and obtain information on regional cortical activity. Coregistration of EEG-NIRS is a recent technique that has been applied for measuring changes in electrical and hemodynamic activity in the human brain. EEG-NIRS coregistration facilitates the avoidance of misleading interpretations of NIRS, particularly in the diagnosis of neurological disorders. In this study, we investigated an approach for enhancing accuracy of NIRS by using EEG to monitor physiological activity during a mental focus task. Using the Wisconsin Card Sorting Test for the subjects mental focus task, we identified two trend types in the EEG and NIRS signals of normal subjects. These data can assist in understanding brain activation statuses and enable determining subjects' degree of mental concentration. If the data can be standardized for the diagnosis of neurological disorders, they can provide a new index to improve traditional methods (e.g., questionnaires) to assist clinical doctors in diagnosing cognitive disorders.
Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation
(2014-01-01)
Chen, Che-Wei
;
Tzeng, Ju-Yuan
;
Chung, Cheng-Ting
;
Chien, Hung-Pin
;
Chien, Chao-Hsin
In this letter, we present a high performance Ge n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiGe Schottky junction source/drain fabricated using phosphorus dopant segregation. Phosphorus atoms were implanted into NiGe and then driven toward the NiGe/p-Ge interface to depin the Fermi level and form a Schottky junction. A high effective barrier height (Phi(Bp)) of 0.57 eV, resulting in a high junction current ratio of >10(4) at the applied voltage vertical bar V-a vertical bar = +/- 1 V. The nMOSFET exhibited a high I-ON/I-OFF ratio of similar to 8 x 10(3) (I-D), similar to 10(5) (I-S), and a subthreshold swing of 138 mV/decade. The nMOSFET developed in this letter exhibited greater transconductance and a drain leakage current that is more than two orders of magnitude lower compared with nMOSFETs with the conventional n(+)/p junction.
Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High I-ON/I-OFF Ratio Ge FinFETs
(2013-06-01)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high I-ON/I-OFF ratio (similar to 5 x 10(5), at V-D = 0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (V-TH) shift can be maintained at the level of similar to 110 mV/V and similar to 0.1 V, respectively, for Ge n-channel FinFET with L-channel = 120 nm and W-Fin = 40 nm. Multifin Ge FinFET with L-channel = 170 nm and W-Fin = 50 nm is also illustrated. Both N-and P-FinFETs possess high I-ON/I-OFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.
Experimental Realization of a Ternary-Phase Alloy Through Microwave-Activated Annealing for Ge Schottky pMOSFETs
(2016-07)
Hsu, Chung-Chun
;
Chi, Wei-Chun
;
Tsai, Yi-He
;
Chou, Chen-Han
;
Chen, Che-Wei
This paper presents a high-performance Ge p-channel MOSFET (pMOSFET) with NiGePt as a ternary-phase alloy of Schottky source/drain (S/D) formed through low-temperature microwave-activated annealing (MWA). We fabricated a NiGePt alloy contact with uniform crystallinity through structural engineering and MWA. We clarified the phenomena of thermal reaction and diffusion for forming ternary-phase alloys using MWA properties such as thermal dynamics and ionic transportation. The ternary-phase NiGePt alloy is crucial for improving the off-leakage current of the junction. A lower process temperature is beneficial for eliminating surface roughness and reducing alloy agglomeration of the Schottky contact S/D. Consequently, the fabricated NiGePt/n-Ge Schottky junction exhibited a high effective barrier height (Phi(Bn)) of 0.59 eV, resulting in a high junction current ratio of more than 10(5) at an applied voltage of vertical bar V-a vertical bar = 1 V. In addition, we exploited the advantages of low-temperature microwave annealing to fabricate the pMOSFET, which includes a GeO2 passivation layer and a Schottky S/D. Our ternary Schottky Ge pMOSFET (L = 4 mu m) exhibited high I-ON/I-OFF ratios of approximately 3.7x10(3)(I-D) and 1.3x10(5)(I-S) and a moderate subthreshold swing of 126 mV/dec.
First Experimental Ge CMOS FinFETs Directly on SOI Substrate
(2012)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
High-performance Ge CMOS FinFETs directly on thin silicon on insulator (SOI) wafer are demonstrated. For the first time, NFET of L-channel = 120nm and Fin width=40nm with high I-on/I-off ratio (>10(5)), excellent drain induced barrier lowering (DIBL) (110mV/V) and subthreshold swing (S. S) (144mV/dec) has been shown. Both Ge n- and p-channel FinFETs with multi-fins have been achieved. Even the NFET of L-channel =90nm exhibits a pretty well on-off behavior after forming gas annealing.
Germanium N and P Multifin Field-Effect Transistors With High-Performance Germanium (Ge) p(+)/n and n(+)/p Heterojunctions Formed on Si Substrate
(2013-04-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Tzeng, Ju-Yuan
;
Li, Pin-Hui
;
Chang, Pang-Sheng
We demonstrate the characteristics of p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction diodes formed by heteroepitaxial Ge grown on Si leading to high performance and very low leakage current. The ON/OFF current ratio of the p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction was >10(7) and >10(6), respectively. The OFF current density was extremely low at <10 mu A/cm(2) for the p(+)-Ge/n-Si formed with different implantation energies of 10 similar to 40 KeV and similar to 20 mu A/cm(2) for the n(+)-Ge/p-Si with different implantation energies of 20 similar to 50 KeV at a reverse bias of vertical bar V-R vertical bar = +/- 1 V, respectively. Both p and n-Ge channel multifin field-effect transistors (FinFETs) were formed by a mesa structure using these p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunctions. A high-kappa/metal gate stack was employed. The body-tied Ge multifin FinFET with a fin width (W-Fin) of similar to 40 nm, and the channel length (L-Channel) was 150 nm for p-FinFET and of 110 nm for n-FinFET, exhibiting a driving current of 174 mu A/mu m at V-G = -2 V and 102 mu A/mu m at V-G = 2 V, respectively. This is the first experimental demonstration of a body-tied high mobility Ge channel multifin FinFET using a top-down approach.
High On/Off Ratio and Very Low Leakage in p(+)/n and n(+)/p Germanium/Silicon Heterojunction Diodes
(2013-02-01)
Chen, Che-Wei
;
Chung, Cheng-Ting
;
Lin, Jyun-Chih
;
Luo, Guang-Li
;
Chien, Chao-Hsin
We demonstrate the characteristics of p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction diodes with a very high on/off ratio and very low leakage current using heteroepitaxial Ge grown directly on Si. The current ratio of p(+)-Ge/n-Si and n(+)-Ge/p-Si heterojunction is similar to 5 x 10(7) and similar to 3 x 10(6), respectively. The remarkably low off current density is 2.1 mu A/cm(2) for p(+)-Ge/n-Si and 19 mu A/cm(2) for n(+)-Ge/p-Si at a reverse bias of vertical bar V-R vertical bar = +/- 1 V, respectively. High on current density (125 A/cm(2) for p(+)-Ge/n-Si and 54 A/cm(2) for n(+)-Ge/p-Si) with a forward bias vertical bar V-F vertical bar = +/- 1 V is obtained with a GeO2 passivation and an Al2O3 isolation. (C) 2013 The Japan Society of Applied Physics
High Performance Ge Schottky PMOSFETs with Ternary-Phase Alloy
(2016-01-01)
Hsu, Chung-Chun
;
Chi, Wei-Chun
;
Chou, Chen-Han
;
Chen, Che-Wei
;
Chien, Hung-Pin
This work demonstrates high-performance Ge p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) [1] with ternary-phase NiGePt alloy Schottky source/drain (S/D) by low-temperature microwave-activated annealing (MWA) [2]. Process flow of Shcottky junctions is shown in Fig. 1. Interestingly, the formed NiGePt alloy is nearly single crystalline. We found the formation of ternary-phase alloy NiGePt seems very helpful in suppressing the off-leakage of junction, as shown in Fig. 2. The fabricated NiGePt/N-Ge Schottky junction depicted an impressive effective barrier height (Phi(Bn)) of similar to 0.59 eV for electrons, leading to a high junction current ratio of >10(5) at the applied voltage of vertical bar V-a vertical bar = 1 V. Slight increase with increasing deposited Pt thickness can be explained by the improved series resistance, as shown in Fig. 2. The lower process temperature of MWA as compared to the conventional thermal annealing is beneficial for eliminating surface roughness, reducing alloy agglomeration of Schottky contact S/D. As a consequence, we employed the advantages of low-temperature MWA to fabricate the Schottky S/D PMOSFETs. With forming gas annealing, the Ge PMOSFET (L = 4 mu m) showed a very high output current of 33.5 mu A/mu m at V-GS-V-T = -2.4 and V-DS = -2 V. Our ternary Schottky PMOSFET exhibited a high I-ON/I-OFF ratios of similar to 3.7 X 10(3)(I-D) and similar to 1.3 X 10(5)(I-S), and a moderate subthreshold swing of 126 mV/dec, as shown in Figs. 3.
High-Performance Germanium p- and n-MOSFETs With NiGe Source/Drain
(2014-08-01)
Chen, Che-Wei
;
Tzeng, Ju-Yuan
;
Chung, Cheng-Ting
;
Chien, Hung-Pin
;
Chien, Chao-Hsin
In this paper, we report Ge p- and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with NiGe source/drain (S/D) with high performance and low leakage current. The forward/reverse current ratio of the NiGe/n-Ge and NiGe/p-Ge junctions were similar to 10(5) and similar to 2 x 10(4) at vertical bar V vertical bar = +/- 1 V, respectively. Interface state densities Dit of Al2O3/GeO2/Ge stack is improved to be around 10(12)/eV(-1) cm(2) near the midgap after forming gas annealing; the gate-stack also shows excellent reliability under constant field stressing. Both p- and n-channel MOSFETs show sufficiently high ION/IOFF ratio. High driving current of similar to 9 and similar to 4 mu A/mu m at vertical bar V-GS - V-T vertical bar = +/-0.8 V and V-DS vertical bar = +/- V is obtained, respectively, for p- and n-MOSFETs. Moreover, S/D series resistance R-SD of the p- and n-MOSFET is reduced by similar to 25% and similar to 42% as compared with that of the transistors with conventional p/n junctions.
High-Performance Schottky Contact Quantum-Well Germanium Channel pMOSFET With Low Thermal Budget Process
(2016-01-01)
Hsu, Chung-Chun
;
Tsai, Yi-He
;
Chen, Che-Wei
;
Li, Jyun-Han
;
Lin, Yu-Hsien
We present a high-performance Si/Ge/Si p-channel metal-oxide-semiconductor field-effect transistor (pMOSFET) with a NiSiGe Schottky junction source/drain (S/D) formed through microwave-activated annealing. A Schottky contact S/D is preferable, because the lower process temperature is beneficial for eliminating Ge diffusion. The fabricated NiSiGe Schottky junction exhibited a high effective barrier height (Phi(Bn)) of 0.69 eV for electrons, resulting in a high junction current ratio of more than 10(5) at the applied voltage of vertical bar V-a vertical bar = 1 V. Our quantum-well pMOSFET exhibited a high I-ON/I-OFF ratio of similar to 10(7) (I-S) and a moderate subthreshold swing of 166 mV/decade.