Browsing by Author "Chen, Chun-Yen"

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800V Ultra-High-Voltage Start-up Mechanism for Pre-regulator in Power Factor Correction (PFC) Controller
(2011)
Chen, Chi-Lin
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Tsai, Jen-Chieh
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Chen, Yi-Ting
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Ni, Chia-Lung
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Chen, Chun-Yen
The on-chip 800V ultra-high-voltage (UHV) start-up mechanism was introduced in this paper. Using the UHV start-up mechanism can minimize the current leakage at the AC input and remove the need of external start-up resistor and capacitor. As a result, the standby current can be decreased to improve the efficiency of AC-DC systems. Furthermore, the zero current detection (ZCD) circuit was used here to ensure the work of the pre-regulator. An inductance coil will detect the primary inductance current and reflect the voltage, which is detected by ZCD circuit to provide the energy to the pre-regulator. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Certainly, high efficiency of 95% can be ensured at the output power of 50W.
92% High Efficiency and Low Current Mismatch Interleaving Power Factor Correction Controller With Variable Sampling Slope and Automatic Loading Detection Techniques
(2013-11-01)
Su, Yi-Ping
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Chen, Chun-Yen
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Ni, Chia-Lung
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Kang, Yu-Chai
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Chen, Yi-Ting
This paper proposes the dual nondeadtime variable sampling slope technique to carry out precise phase sensing and suppress phase error in interleaving power factor correction (PFC) controller over a whole ac switching cycle for low current mismatch. Furthermore, the proposed automatic loading detection (ALD) technique can keep efficiency higher than 92% over a wide load range due to accurately controlling the ON/OFF of dual phases. The test circuit fabricated in the TSMC 0.5-mu m 800-V UHV process shows that the highly integrated interleaving PFC can deliver a high power of 180 W and a high efficiency of 95% at an output power of 180 W.
A Two-Directional BigData Sorting Architecture on FPGAs
(2020-01-01)
Lai, Bo-Cheng
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Chen, Chun-Yen
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Hsin, Yi-Da
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Lin, Bo-Yen
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電子工程學系及電子研究所
Sorting is pivotal data analytics and becomes challenging with intensive computation on drastically growing data volume. Sorting on FPGA has shown superior throughput, but the limited in-system memory causes vast data transferring to/from external storage when handling a large dataset. We propose a two-directional sorting (2DSort) architecture which sorts data sequences on both horizontal and vertical directions. 2DSort significantly reduces the costly data transmission by tracking the data on FPGA and writes back the data to external storage when the final sorting position is determined. 2DSort shows average 38.5 percent runtime enhancement in comparison to state-of-the-art bigdata sorting engine on FPGA.
Automatic Loading Detection (ALD) Technique for 92% High Efficiency Interleaving Power Factor Correction (PFC) Over a Wide Output Power of 180W
(2012)
Tsai, Jen-Chive
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Chen, Chun-Yen
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Chen, Yi-Ting
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Ni, Chia-Lung
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Su, Yi-Ping
the proposed automatic loading detection (ALD) technique keeps high efficiency in interleaving power factor correction (PFC) over a wide load range. With the advantages of small input/output filter and output ripple in the interleaving mechanism, the improved efficiency by the ALD technique at light loads due to reduced switching loss can be widely used in the adapter of portable electronics. The ALD technique can calculate the power by the detection of peak input voltage to reduce the switching loss since the slave channel can be completely turned off for power saving at light loads. Therefore, the boundary control mode (BCM) control can simultaneously provide high power and keep high conversion efficiency both at light and heavy loads. The highly integrated PFC controller fabricated in TSMC 800V UHV process shows high efficiency of 92% over a wide output power of 180 W.
Boundary Conduction Mode Controlled Power Factor Corrector With Line Voltage Recovery and Total Harmonic Distortion Improvement Techniques
(2014-07-01)
Su, Yi-Ping
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Ni, Chia-Lung
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Chen, Chun-Yen
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Chen, Yi-Ting
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Tsai, Jen-Chieh
The proposed line voltage recovery (LVR) and the total harmonic distortion improvement (THDI) technique improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range in boundary conduction mode controlled power factor corrector (PFC). The LVR detects the input line root-mean-square voltage to generate the digital equivalent code to the THDI for optimizing the THD by tuning the on-time value at different line voltages. In addition, the LVR and the THDI provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC controller can keep high PF and low THD over a wide line voltage. Experimental results demonstrate that the peak PF value is 0.998 and the minimum THD is 1.7% by the test circuit fabricated in a TSMC 800-V ultrahigh-voltage process with the universal line voltage range of 90-264 V.
Characterization of a heat-tolerant Chlorella sp GD mutant with enhanced photosynthetic CO2 fixation efficiency and its implication as lactic acid
(2017-09-12)
Lee, Tse-Min
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Tseng, Yu-Fei
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Cheng, Chieh-Lun
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Chen, Yi-Chuan
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Lin, Chih-Sheng
Background: Fermentative production of lactic acid from algae-based carbohydrates devoid of lignin has attracted great attention for its potential as a suitable alternative substrate compared to lignocellulosic biomass. Results: A Chlorella sp. GD mutant with enhanced thermo-tolerance was obtained by mutagenesis using N-methyl-N'-nitro-N-nitrosoguanidine to overcome outdoor high-temperature inhibition and it was used as a feedstock for fermentative lactic acid production. The indoor experiments showed that biomass, reducing sugar content, photosynthetic O-2 evolution rate, photosystem II activity (F-v/F-m and F-v'/F-m'), and chlorophyll content increased as temperature, light intensity, and CO2 concentration increased. The mutant showed similar DIC affinity and initial slope of photosynthetic light response curve (a) as that of the wild type but had higher dissolved inorganic carbon (DIC) utilization capacity and maximum photosynthesis rate (P-max). Moreover, the PSII activity (F-v'/F-m') in the mutant remained normal without acclimation process after being transferred to photobioreactor. This suggests that efficient utilization of incident high light and enhanced carbon fixation with its subsequent flux to carbohydrates accumulation in the mutant contributes to higher sugar and biomass productivity under enriched CO2 condition. The mutant was cultured outdoors in a photobioreactor with 6% CO2 aeration in hot summer season in southern Taiwan. The harvested biomass was subjected to separate hydrolysis and fermentation (SHF) for lactic acid production with carbohydrate concentration equivalent to 20 g/L glucose using the lactic acid-producing bacterium Lactobacillus plantarum 23. The conversion rate and yield of lactic acid were 80% and 0.43 g/g Chlorella biomass, respectively. Conclusions: These results demonstrated that the thermo-tolerant Chlorella mutant with high photosynthetic efficiency and biomass productivity under hot outdoor condition is an efficient fermentative feedstock for large-scale lactic acid production.
CRAXDroid: Automatic Android System Testing by Selective Symbolic Execution
(2014-01-01)
Yeh, Chao-Chun
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Lu, Han-Lin
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Chen, Chun-Yen
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Khor, Kee-Kiat
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Huang, Shih-Kun
Mobile devices such as smart phones and tablet PCs are becoming common personal devices. The business model of a central software market is also thriving and turning into a major distribution source of software packages on those devices. However, these devices often contain personal private information and can be used to conduct operations involving data leakage and payment events like sending SMS. As a result, the quality of software on mobile devices becomes a critical issue. We aim at checking whether software off the shelf contains defective behavior or potential vulnerabilities, and aiding the official APP or third party markets to ensure their software without privacy issues. We have built a platform for android APP testing, by revising our software quality assurance and exploit generation platform, called CRAX, to apply in the Android platform. It is called the CRAXDroid that allows any inputs to be the testing sources to the APP without source code. These approaches are based on the symbolic execution technique and android emulator. By automatically exploring execution paths, we can find potential software defects. We perform several experiments on Android applications to prove the feasibility of our method.
Divergent Synthesis of 48 Heparan Sulfate-Based Disaccharides and Probing the Specific Sugar-Fibroblast Growth Factor-1 Interaction
(2012-12-26)
Hu, Yu-Peng
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Zhong, Yong-Qing
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Chen, Zhi-Geng
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Chen, Chun-Yen
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Shi, Zhonghao
Several biological processes involve glycans, yet understanding their ligand specificities is impeded by their inherent diversity and difficult acquisition. Generating broad synthetic sugar libraries for bioevaluations is a powerful tool in unraveling glycan structural information. In the case of the widely distributed heparan sulfate (HS), however, the 48 theoretical possibilities for its repeating disaccharide call for synthetic approaches that should minimize the effort in an undoubtedly huge undertaking. Here we employed a divergent strategy to afford all 48 HS-based disaccharides from just two orthogonally protected disaccharide precursors. Different combinations and sequence of transformation steps were applied with many downstream intermediates leading up to multiple target products. With the full disaccharide library in hand, affinity screening with fibroblast growth factor-1 (FGF-1) revealed that four of the synthetic sugars bind to FGF-1. The molecular details of the interaction were further clarified through X-ray analysis of the sugar-protein cocrystals. The capability of comprehensive sugar libraries in providing key insights in glycan-ligand interaction is, thus, highlighted.
High-PF and Ultra-Low-THD Power Factor Correction Controller by Sinusoidal-Wave Synthesis and Optimized THD Control
(2013)
Chang, Chih-Wei
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Ni, Chia-Lung
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Tsai, Jen-Chieh
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Chen, Yi-Ting
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Chen, Chun-Yen
the proposed sinusoidal-wave synthesis (SWS) and the optimized THD control (OTC) improve power factor (PF) and total harmonic distortion (THD) over a wide line voltage range. The SWS detects the input line root-mean-square (rms) voltage to generate the digital equivalent code to the OTC for optimizing the THD by tuning the on-time value. Besides, the SWS and the OTC provide a feedforward path to reduce the ripple of the feedback voltage for further improving the THD. Therefore, the PFC converter can keep high PF and low THD over a wide line voltage. Experimental results demonstrate the PF is higher than 0.99 and the THD is 1.7% at V-AC of 90 - 110V by the test circuit fabricated in TSMC 800V UHV process.
Perturbation On-time (POT) Control and Inhibit Time Control (ITC) in Suppression of THD of Power Factor Correction (PFC) Design
(2011)
Tsai, Jen-Chieh
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Chen, Chi-Lin
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Chen, Yi-Ting
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Ni, Chia-Lung
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Chen, Chun-Yen
The paper presented the perturbation on-time (POT) control technique to suppress the total harmonic distortion (THD) to improve the performance of the power factor correction (PFC) in the AC-DC converter. Simultaneously, it can improve the efficiency through the proposed inhibit time control (ITC) mechanism at low AC input voltage. The test circuit fabricated in TSMC 800V UHV process can show the highly-integrated PFC controller. Experimental results demonstrate low THD of 8%, which results in high PF of 99%. Besides, high efficiency of 95% can be ensured at the output power of 90W.
Perturbation On-Time (POT) Technique in Power Factor Correction (PFC) Controller for Low Total Harmonic Distortion and High Power Factor
(2013-01-01)
Tsai, Jen-Chieh
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Chen, Chi-Lin
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Chen, Yi-Ting
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Ni, Chia-Lung
;
Chen, Chun-Yen
The proposed perturbation on-time technique suppresses total harmonic distortion (THD) and, thus, improves the power factor in the power factor correction (PFC) controller. Besides, the adaptive control of the minimum off time by the proposed inhibit time control can improve efficiency even at low ac input voltage. Therefore, highly integrated PFC converter fabricated in the TSMC 800-V ultrahigh voltage process can achieve low THD of 6%, high PF of 99%, and high efficiency of 95% at the output power of 90 W.
Preliminary clinical and radiographic outcomes of proximal humeral fractures: comparison of ALPS and PHILOS plating in Asian patients in Taiwan
(2020-08-28)
Chen, Chun-Yen
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Chang, Hao-Wei
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Hsieh, Shang-Lin
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Chang, Chien-Chun
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Tsai, Chun-Hao
Background Up to 20% of proximal humeral fractures need to be treated operatively. However, numerus complications were reported by using fixed angled locking plates. The ALPS Proximal Humerus Plating System is a new design implant with novel design features. The aim of this study was to compare the preliminary clinical outcomes and complications of proximal humeral fractures treated with either ALPS or the proximal humeral internal locking system (PHILOS) in Asian patients in Taiwan. Methods Between January 2016 and December 2018, 66 patients with displaced proximal humeral fractures were analyzed retrospectively, of whom 31 underwent ALPS implant treatment and 35 underwent PHILOS implant treatment. Intraoperative blood loss and operation time, postoperative Constant-Murley Shoulder Outcome (Constant-Murley) score, and complications variables were recorded for the comparison. All cases were regularly followed up for at least 1 year. Results The mean follow-up period was 400.8 days (range, 367-446 days). Union was achieved in 98.5% of patients (65/66). The ALPS group yielded similar radiologic and clinical outcomes to the PHILOS plating group for treating displaced proximal humeral fractures, including operation time, intraoperative blood loss, the Constant-Murley score, and varus malunion (P> 0.05, respectively). However, the incidence of total postoperative complications in the ALPS group was significantly lower than in the PHILOS group (P< 0.05). There was a trend of a lower complication rate of screws/pegs protrusion, avascular necrosis, subacromial impingement, postoperative infection, and reoperation in the ALPS group, although it was not statistically significant (P> 0.05, respectively). Conclusion The ALPS group yielded similar radiologic and clinical outcomes to the PHILOS plating group for displaced proximal humeral fractures, but the ALPS group had a significantly lower total rate of complications. Therefore, ALPS may be a better option for treating proximal humeral fractures. Further larger clinical studies are needed to confirm the findings presented here.
Time-Shift Current Balance Technique in Four-Phase Voltage Regulator Module with 90% Efficiency for Cloud Computing
(2015-03-01)
Su, Yi-Ping
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Chen, Wei-Chung
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Huang, Yu-Ping
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Chen, Chun-Yen
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Ni, Chia-Lung
Four power stages for voltage regulator module (VRM) are adopted to provide high current driving capability and low output ripple in cloud computing. Thus, the time-shift current balance (TSCB) technique is proposed to achieve high performance power supply for servers. In addition, the power request, which includes the number of active phases and voltage identification, is acknowledged by servers for high driving capability during high throughput and high efficiency during standby mode. Furthermore, to equally distribute the current in each phase, the proposed TSCB technique in either voltage-mode or peak current-mode control improves the current balance performance and solves the stability problem. In the scale-down clouding computing prototype, the efficiency can be kept higher than 90% over a wide load current range of 2 A. In addition, the performance and operating frequency of the servers in stable operation are not limited by the VRM with the TSCB technique.
Triple Loop Modulation (TLM) for High Reliability and Efficiency in a Power Factor Correction (PFC) System
(2013-07-01)
Tsai, Jen-Chieh
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Ni, Chia-Lung
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Chen, Chi-Lin
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Chen, Yi-Ting
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Chen, Chun-Yen
The proposed triple loop modulation (TLM) can ensure reliability of the power factor correction (PFC) system due to the improvement of transient response. In conventional design, low bandwidth of less than 20Hz that rejects ac source of 60/120 Hz coupling deteriorates system reliability in case of output load variation. Contrarily, the proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current to shorten transient response time. Besides, in the steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by the TLM. The test circuit fabricated in a VIS 500 V UHV laterally diffused metal-oxide-semiconductor transistor process demonstrates that the highly integrated PFC controller with the proposed TLM has high power factor of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than in conventional PFC design with output load variation from 90 to 20W and vice versa.
Triple Loop Modulation (TLM) for High Reliability and Efficiency in Power Factor Correction (PFC) System
(2012)
Tsai, Jen-Chieh
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Ni, Chia-Lung
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Chen, Chun-Yen
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Chen, Yi-Ting
;
Chen, Chi-Lin
Reliability of the Power Factor Correction (PFC) system was improved by fast transient response using the proposed triple loop modulation (TLM). Low bandwidth of less than 20 Hz that rejects AC source of 60/120 Hz coupling deteriorated system reliability in case of output load variation. The proposed TLM can automatically adjust bandwidth to rapidly increase or decrease inductor current in order to shorten transient response time. In steady state, system stability can be guaranteed by low-frequency compensation pole without being affected by TLM. The test circuit fabricated in VIS 500 V UHV LDMOS process demonstrated the performance of the highly-integrated PFC controller with the proposed TLM. Experimental results showed that the PFC system with TLM has high PF of 99%, high efficiency of 95%, and high power driving capability of about 90 W. The improvement in transient response is twofold faster than conventional PFC design with output load variation from 90W to 45 W and vice versa.
Variable Sampling Slope (VSS) and No-Deadtime Ramp Generator (NDRG) Techniques for Closed-Loop Interleaving Power Factor Correction (PFC) Design with Suppression of Current Mismatch
(2012)
Chen, Chun-Yen
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Peng, Ruei Hong
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Tsai, Jen-Chieh
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Kang, Yu-Chi
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Ni, Chia-Lung
the proposed interleaving power factor correction (PFC) can effectively reduce the size of the AC-DC converter for portable electronics. Fully integrated variable sampling slope (VSS) technique can provide precise phase regulation under variable line voltage. Besides, the no-deadtime ramp generator (NDRG) records the previous status to modify the sequent on-time value to achieve current sharing for suppressing the total harmonic distortion (THD) and restraining the input current ripple, EMI filter, and the size of input inductor. Therefore, more power can be provided by the proposed interleaving PFC than that of single-phase PFC. Simultaneously, the drawback of the peak current twice than the average current in the Boundary control mode (BCM) can be greatly reduced. The test circuit fabricated in the TSMC 0.5 mu m 800V UHV process shows the highly integrated interleaving PFC can deliver high power of 180W with improved phase regulation precision.