Browsing by Author "Chen, Hung-Bin"

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A 2-bit/Cell Gate-All-Around Flash Memory of Self-Assembled Silicon Nanocrystals
(2013-02-01)
Chen, Hung-Bin
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Chang, Chun-Yen
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Hung, Min-Feng
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Tang, Zih-Yun
;
Cheng, Ya-Chi
This work presents gate-all-around (GAA) polycrystalline silicon (poly-Si) nanowires (NWs) channel poly-Si/SiO2/Si3N4/SiO2/poly-Si (SONOS) nonvolatile memory (NVM) with a self-assembled Si nanocrystal (Si-NC) embedded charge trapping (CT) layer. Fabrication of the Si-NCs is simple and compatible with the current flash process. The 2-bit operations based on channel hot electrons injection for programming and channel hot holes injection for erasing are clearly achieved by the localized discrete trap. In the programming and erasing characteristics studies, the GAA structure can effectively reduce operation voltage and shorten pulse time. One-bit programming or erasing does not affect the other bit. In the high-temperature retention characteristics studies, the cell embedded with Si-NCs shows excellent electrons confinement vertically and laterally. With respect to endurance characteristics, the memory window does not undergo closure after 10(4) program/erase (P/E) cycle stress. The 2-bit operation for GAA Si-NCs NVM provides scalability, reliability and flexibility in three-dimensional (3D) high-density flash memory applications. (C) 2013 The Japan Society of Applied Physics
A Highly Scalable Poly-Si Junctionless FETs Featuring a Novel Multi-Stacking Hybrid P/N Layer and Vertical Gate with Very High Ion/Ioff for 3D Stacked ICs
(2016)
Cheng, Ya-Chi
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Chen, Hung-Bin
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Chang, Chun-Yen
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Cheng, Chun-Hu
;
Shih, Yi-Jia
This work demonstrates for the first time a three-dimensional (3D) stacked hybrid P/N layer for p-channel junctionless thin-film transistor (JL-TFT) with nanowire (NW) structures. Relative to conventional stacked devices, the 3D stacked hybrid P/N JL-TFT exhibits a high I-on/I-off current ratio (> 10(9)), a steep subthreshold swing (SS) of 70 mV/dec, a low drain-induced barrier lowering (DIBL) value of 3.5 mV/V; these properties are achieved by reducing the effective channel thickness that is determined by the channel/substrate junction. The developed stacked hybrid P/N exhibits reduced low-frequency noise, less sensitive temperature coefficients and performance variation in both threshold voltage (Vth) and SS, and so is suit for high-density 3D stacked integrated circuit (IC) applications.
A Novel Cost Effective Double Reduced Surface Field Laterally Diffused Metal Oxide Semiconductor Design for Improving Off-State Breakdown Voltage
(2012-04-01)
Han, Ming-Hung
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Chen, Hung-Bin
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Chang, Chia-Jung
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Wu, Jia-Jiun
;
Chen, Wen-Chong
In this work, double reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device combines a new implant technology without using additional mask in standard 0.18 mu m technology has been proposed and successfully fabricated. The breakdown voltage (BV) can be improved significantly with simply changing the implanted region length in this implant technology. Firstly, hydrodynamic transport simulations which analyze the high bias condition electric field distributions are examined to predict and explain the increase of breakdown voltage. Then the fabricated devices process flow is demonstrated, the structures are performed, and the breakdown voltages increase with different n-type double diffusion (NDD) photoresistor (PR) size using the change of PR exposure dose are investigated. The measurement results show that maximum NDD PR size achieves BV improvement of 6.3%, and 5% increase of figure of merit (FOM) evaluation. Throughout the whole fabrication process, no additional mask and device area show the potential of cost effective with the proposed technique. Such devices with good off-state breakdown voltage and specific on-resistance are very competitive with similar technologies and show good promising in system on chip (SOC) applications. (C) 2012 The Japan Society of Applied Physics
Back-gate bias effect on nanosheet hybrid P/N channel of junctionless thin-film transistor with increased I-on versus decreased I-off
(2015-11-02)
Cheng, Ya-Chi
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Chen, Hung-Bin
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Chang, Chun-Yen
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Wu, Yi-Kang
;
Shih, Yi-Jia
A hybrid P/N channel junctionless (JL) thin-film transistor (TFT) with back-gate bias (V-bg) has been demonstrated. By applying negative bias of V-bg = -8V in gate length of 50 nm shows excellent SS (<90 mV/dec), a negligible drain induced barrier lowering (DIBL), increased I-on versus decreased I-off (ratio > 10(8)), and high V-th modulation. The increased I-on simultaneously decreased I-off via negative V-bg is attributed to smaller surface E-field at ON-state, significantly reducing the impact on interface traps and thinner effective channel thickness at OFF-state, improving gate controllability. Hence, hybrid P/N JL-TFT with V-bg is a promising for low power circuit, power management, and System-on-Chip applications. (C) 2015 AIP Publishing LLC.
Characteristic of p-Type Junctionless Gate-All-Around Nanowire Transistor and Sensitivity Analysis
(2013-02-01)
Han, Ming-Hung
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Chang, Chun-Yen
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Jhan, Yi-Ruei
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Wu, Jia-Jiun
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Chen, Hung-Bin
The characteristics and sensitivities of p-type junctionless (JL) gate-all-around (GAA) (JLGAA) nanowire transistors are demonstrated by simulating a 3-D quantum transport device with a view to their use in CMOS technology. The concentration of dopants in a p-type JL nanowire transistor is not as high as that in an n-type device owing to solid solubility of boron in silicon. However, we can use a midgap material as gate electrode to design an appropriate device threshold voltage. The p-type JLGAA transistor exhibits a favorable on/off current ratio and better short-channel characteristics than a conventional inversion-mode transistor with a GAA structure. Sensitivity analyses reveal that the channel thickness and random dopant fluctuation substantially affect the device performance in terms of threshold voltage (V-th), on current (I-on), and subthreshold slope because of the full depletion condition of the channel. The channel length and oxide thickness have less impact because the short-channel effect is well controlled.
Characteristics of a Novel Poly-Si P-Channel Junctionless Thin-Film Transistor With Hybrid P/N-Substrate
(2015-02-01)
Cheng, Ya-Chi
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Chen, Hung-Bin
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Su, Jun-Ji
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Shao, Chi-Shen
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Thirunavukkarasu, Vasanthan
This letter for the first time proposes a hybrid P/N substrate as a poly-Si p-channel for junctionless thin-film transistor (JL-TFT) with nanowires and omega-gate structures. The hybrid P/N JL-TFT exhibits a high I-ON/I-OFF current ratio (>10(7)), a steep subthreshold swing of 64 mV/dec, and a low drain-induced barrier lowering value of 3 mV/V by reducing the effective channel thickness that is caused by the channel/substrate junction. In addition, the series resistance for novel P/N JL-TFT with channel thickness (T-ch) of 24 nm is 50 times smaller than conventional JL-TFT with T-ch = 12 nm. This hybrid P/N structure can break through the strict limitation of JL-TFT channel thickness.
Characteristics of Gate-All-Around Junctionless Poly-Si TFTs With an Ultrathin Channel
(2013-07-01)
Chen, Hung-Bin
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Chang, Chun-Yen
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Lu, Nan-Heng
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Wu, Jia-Jiun
;
Han, Ming-Hung
This letter demonstrates for the first time junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with ultrathin channels (2 nm). The subthreshold swing is 61 mV/decade and the ON/OFF current ratio is close to 10(8) because of the excellent gate controllability and ultrathin channel. The JL-GAA TFTs have a low drain-induced barrier lowering value of 6 mV/V, indicating greater suppression of the short-channel effect than in JL-planar TFTs. The cumulative distribution of electrical parameters in JL-GAA is small. Therefore, the proposed JL-GAA TFTs of excellent device characteristics along with simple fabrication are highly promising for future system-on-panel and system-on-chip applications.
Characterizing the electrical properties of raised S/D junctionless thin-film transistors with a dual-gate structure
(2014-12-11)
Cheng, Ya-Chi
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Chen, Hung-Bin
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Su, Jun-Ji
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Shao, Chi-Shen
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Wang, Cheng-Ping
This letter demonstrates a p-type raised source-and-drain (raised S/D) junctionless thin-film transistors (JL-TFTs) with a dual-gate structure. The raised S/D structure provides a high saturation current (> 1 mu A/mu m). The subthreshold swing (SS) is 100 mV/decade and the drain-induced barrier lowering (DIBL) is 0.8 mV/V, and the I-on/I-off current ratio is over 10(8) A/A for L-g = 1 mu m. Using a thin channel structure obtains excellent performance in the raised S/D structure. Besides the basic electrical characteristics, the dual-gate structure can also be used to adjust V-th in multi-V-th circuit designs. This study examines the feasibility of using JL-TFTs in future three-dimensional (3D) layer-to-layer stacked high-density device applications.
Device and Circuit Performance Estimation of Junctionless Bulk FinFETs
(2013-06-01)
Han, Ming-Hung
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Chang, Chun-Yen
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Chen, Hung-Bin
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Cheng, Ya-Chi
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Wu, Yung-Chun
The design and characteristics of junctionless (JL) bulk FinFET devices and circuits are compared with the conventional inversion-mode (IM) bulk FinFET using 3-D quantum transport device simulation. The JL bulk FinFET shows better short channel characteristics, including drain-induced barrier lowering, subthreshold slope, and threshold voltage (V-th) roll-off characteristics at supply voltage (V-DD) 1 V. Analyses of electron density and electric field distributions in ON-state and OFF-state also show that the JL devices have better ON-OFF current ratios. Regarding design aspects, the effects of channel doping concentration (N-ch) and Fin height (H)/width (W) on device V-th are also compared. In addition, the V-th of the proposed JL bulk FinFET can be easily tuned by an additional parameter, substrate doping concentration (N-sub). Inverter performance and static random access memory (SRAM) circuit performance are also compared using a coupled device-circuit simulation. The high-to-low delay time (t(HL)) and low-to-high delay time (t(LH)) of the inverter with JL bulk FinFET are smaller than the inverter with IM bulk FinFET. The JL bulk FinFET SRAM cell also provides a similar static transfer characteristic to those of IM bulk FinFET SRAM cell, which show large potential in digital circuit application.
High voltage characteristics of junctionless poly-silicon thin film transistors
(2013-09-16)
Cheng, Ya-Chi
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Wu, Yung-Chun
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Chen, Hung-Bin
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Han, Ming-Hung
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Lu, Nan-Heng
The breakdown voltage (V-BD) and breakdown mechanism of junctionless (JL) poly-Si thin film transistor (TFT) were compared to the conventional inversion-mode (IM) TFT using fabricated devices and 3D quantum-corrected hydrodynamic transport device simulation. The simulated results are correspondent with experimental ones. The analyses of electric field distributions in on-state show that the channel of JL devices can equally share the voltage like a resistor, because there are no junctions formed between channel and source/drain. The JL TFT shows excellent breakdown characteristics; the off-state V-BD of 53.4V is several times larger than V-BD of 9.5V in IM TFT with same device size. JL devices have large potential for high voltage power metal-oxide-semiconductor devices and circuit applications. (C) 2013 AIP Publishing LLC.
High-Reliability Trigate Poly-Si Channel Flash Memory Cell With Si-Nanocrystal Embedded Charge-Trapping Layer
(2012-04-01)
Chen, Hung-Bin
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Wu, Yung-Chun
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Chen, Lun-Chun
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Chiang, Ji-Hong
;
Yang, Chao-Kan
This letter introduces a polycrystalline-silicon nanowire (NW) thin-film nonvolatile memory (NVM) with a self-assembled silicon-nanocrystal (Si-NC) embedded charge-trapping (CT) layer. This process is simple and compatible with conventional CMOS processes. Experimental results indicate that this NW NVM exhibits high reliability due to a deep-quantum-well structure and immunity of enhanced electric field underneath a disk-shaped Si-NC. After 10 000 P/E cycles, the memory window loss of the NVM with a Si-NC embedded CT layer is less than 12% until 10(4) s at 150 degrees C. Accordingly, a poly-Si thin-film transistor with a Si-NC embedded CT layer is highly promising for NVM applications.
Improving Breakdown Voltage of LDMOS Using a Novel Cost Effective Design
(2013-05-01)
Han, Ming-Hung
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Chen, Hung-Bin
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Chang, Chia-Jung
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Tsai, Chi-Chong
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Chang, Chun-Yen
A reduced surface field (RESURF) laterally diffused metal oxide semiconductor (LDMOS) device with the concept of charge compensation using p-implant layer (PIL) without additional process step is proposed in standard 0.18-mu m technology. By simply using the p-type drift drain (PDD) implantation of p-type LDMOS into n-type LDMOS, breakdown voltage (VBD) is substantially improved. For a thorough study of device phenomena, hydrodynamic transport simulations are first performed to analyze the electric field distributions at high voltage bias in order to explain increases in breakdown voltage and predict its optimal design parameter. Then fabrication of the devices is performed and shows that the breakdown voltages increase significantly. The measurement results show a 12% improvement in VBD and a 5% improvement in figure of merit (FOM). Throughout the fabrication process, the enlarged breakdown voltage obtained by the PIL without additional process and device area show the potential of cost effective. Because such devices have good off-state breakdown voltage and specific on-resistance, they are very competitive with similar technologies and promising system-on-chip (SOC) applications.
Low-Voltage Programmable Gate-All-Around (GAA) Nanosheet TFT Nonvolatile Memory Using Band-to-Band Tunneling Induced Hot Electron (BBHE) Method
(2019-01-01)
Chen, Lun-Chun
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Chen, Hung-Bin
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Chang, Yu-Shuo
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Lin, Shih-Han
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Han, Ming-Hung
A low-voltage programmable gate-all-around (GAA) nanosheet poly-Si thin-film transistor (TFT) nonvolatile memory (NVM), which uses band-to-band tunneling induced hot electron (BBHE) programming, is demonstrated. The BBHE method is extremely efficient for programming data in the p-type GAA nanosheet TFT NVM because the GAA nanosheet structure enhances the source-to-drain component of the electric field in its channel. Therefore, the enhanced electric field of the BBHE phenomenon creates energetic electrons that surmount the tunneling oxide barrier easily and pass shallow traps in the charge trapping layer of the GAA TFT NVM. Consequently, the p-type GAA TFT NVM achieves low-voltage programming bias and satisfactory data retention.
Performance Comparison Between Bulk and SOI Junctionless Transistors
(2013-02-01)
Han, Ming-Hung
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Chang, Chun-Yen
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Chen, Hung-Bin
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Wu, Jia-Jiun
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Cheng, Ya-Chi
The design and characteristics of a junctionless (JL) bulk FinFET were compared with the silicon-on-insulator (SOI) JL nanowire transistor (JNT) using 3-D quantum transport device simulation. The JL bulk FinFET exhibits a favorable ON/OFF current ratio and short-channel characteristics by reducing the effective channel thickness that is caused by the channel/substrate junction. The drain-induced barrier lowering and the subthreshold slope are about 40 mV and 73 mV/dec, respectively, with an ON/OFF current ratio of 10(5) at W = 10 nm. The JL bulk FinFET is less sensitive to the channel thickness than the SOI JNT. Furthermore, the threshold voltage V-th of the JL bulk FinFET can be easily tuned by varying substrate doping concentration N-sub. The modulation range of V-th as N-sub changes from 10(18) to 10(19) cm(-3), which is around 30%.
Performance Enhancement of a Novel P-type Junctionless Transistor Using a Hybrid Poly-Si Fin Channel
(2014)
Cheng, Ya-Chi
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Chen, Hung-Bin
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Shao, Chi-Shen
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Su, Jun-Ji
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Wu, Yung-Chun
The hybrid poly-Si fin channel junctionless (JL) field-effect transistors (FET) are fabricated first. This novel devices show stable temperature/reliability characteristics, and excellent electrical performances in terms of a steep SS (64mV/dec), a high I-on/I-off current ratio (>10(7)) and a small DIBL (3mV/V) by reducing the effective channel thickness that is caused by the hybrid P+ channel and n-type substrate (hybrid P/N) junction. In addition, the novel P/N JL-TFT shows smaller series resistance and less current crowding than convectional JL-TFT with ultra-thin channel. Furthermore, our device can be supported by simulated results using technology computer-aided design (TCAD) simulation. Hence, the proposed hybrid P/N JL-TFTs are highly promising for future further scaling.
Reliability Study on Tri-Gate Nanowires Poly-Si TFTs under DC and AC Hot-Carrier Stress
(2007)
Wu, Yung-Chun
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Chen, Hung-Bin
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Feng, Li-Wei
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Chang, Ting-Chang
;
Liu, Po-Tsun
This work studies reliability after dc and ac hot-carrier stress of polysilicon thin-film transistors (poly-Si TFTs) with single-channel and ten-nanowire channels, respectively. For single-channel (S1) poly-Si TFT, the device characteristics degradation under ac hot-carrier stress is severer than dc stress. In addition, the V-th and SS variation increases with the frequency increasing from 1 K Hz to 1 MHz. On the contrary, for tennanowire channels (M10) tri-gate poly-Si TFT, the V-th and SS variation is much lower than the S1 TFT with different stressing frequency. These results indicate that the M10 TFT has less deep state generation after dc and ac stress. Because the M10 TFT has more effective NH3 plasma passivation than that of S1 TFT due to the ten split nanowire channels has wide NH3 plasma passivation area. Moreover, M10 TFT has robust tri-gate control can reduce the lateral electrical field and its penetration from the drain to reduce hot-carrier effect. In ac stress study, the device degradation is dependent on the pulse failing time rather than rising time. In temperature study, the device degradation is improved as the operation temperature increasing from 25 degrees C to 75 degrees C.
Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor
(2014-08-13)
Cheng, Ya-Chi
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Chen, Hung-Bin
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Han, Ming-Hung
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Lu, Nan-Heng
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Su, Jun-Ji
The high temperature dependence of junctionless (JL) gate-all-around (GAA) poly-Si thin-film transistors (TFTs) with 2-nm-thick nanosheet channel is compared with that of JL planar TFTs. The variation of SS with temperature for JL GAA TFTs is close to the theoretical value (0.2 mV/dec/K), owing to the oxidation process to form a 2-nm-thick channel. The bandgap of 1.35 eV in JL GAA TFTs by fitting experimental data exhibits the quantum confinement effect, indicating greater suppression of I-off than that in JL planar TFTs. The measured partial derivative V-th/partial derivative T of -1.34 mV/degrees C in JL GAA nanosheet TFTs has smaller temperature dependence than that of -5.01 mV/degrees C in JL planar TFTs.
Temperature-dependent characteristics of junctionless bulk transistor
(2013-09-23)
Han, Ming-Hung
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Chen, Hung-Bin
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Yen, Shiang-Shiou
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Shao, Chi-Shen
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Chang, Chun-Yen
The temperature-dependent performance, including drain current (I-d) and gate capacitance (C-gg) of multi-gate junctionless (JL) bulk transistor for temperature (T) ranging from 150 K to 500 K, was investigated using 3D thermodynamic quantum-corrected device simulation. The combination effect of impurity scattering and phonon scattering is observed owing to the different temperature-dependent of mobility at low and high temperature. Since the C-gg of the JL device consists of a series combination of oxide capacitance (C-ox) and semiconductor channel capacitance (C-S) due to bulk conduction of the current, the C-gg at on-state (V-g = 1 V) shows much sensitive to the temperature than a conventional inversion-mode transistor. (C) 2013 AIP Publishing LLC.