Browsing by Author "Chen, Wen-Yi"

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A BENDING N-WELL BALLAST LAYOUT TO IMPROVE ESD ROBUSTNESS IN FULLY-SILICIDED CMOS TECHNOLOGY
(2010)
Wen, Yong-Ru
;
Ker, Ming-Dou
;
Chen, Wen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Ballast technique has been reported as a cost effective method to improve ESD robustness of fully-silicided devices without using silicide block. In this work, a new ballast technique, the bending N-Well (BNW) ballast structure, is proposed to enhance ESD robustness of fully-silicided NMOS. With a deep N-Well to cover the fully-silicided NMOS with BNW ballast structure, ESD robustness of the NMOS can be further improved by enhancing the turn-on uniformity among the multi-fingers of the NMOS.
A simple approach toward low-dielectric polyimide nanocomposites: Blending the polyimide precursor with a fluorinated polyhedral oligomeric silsesquioxane
(2008-09-15)
Ye, Yun-Sheng
;
Yen, Ying-Chieh
;
Chen, Wen-Yi
;
Cheng, Chih-Chia
;
Chang, Feng-Chih
This article describes a new and simple method for preparing polyimide nanocomposites that have very low dielectric constants and good thermal properties: simply through blending the polyimide precursor with a fluorinated polyhedral oligomeric silsesquioxane derivative, octakis(dimethylsiloxyhexafluoropropyl) silsesquioxane (OF). The low polarizability of OF is compatible with polyimide matrices, such that it can improve the dispersion and free volume of the resulting composites. Together, the higher free volume and lower polarizability of OF are responsible for the lower dielectric constants of the PI-OF nanocomposites. This simple method for enhancing the properties of polyimides might have potential applicability in the electronics industry. (C) 2008 Wiley Periodicals, Inc.
Characterization of SOA in Time Domain and the Improvement Techniques for Using in High-Voltage Integrated Circuits
(2012-06-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Safe operating area (SOA) in power semiconductors is one of the most important factors affecting device reliability. The SOA region of power MOSFETs must be well characterized for using in circuit design to meet the specification of applications, particularly including the time domain of circuit operations. In this paper, the characterization of SOA in the time domain is performed with the experimental measurement on silicon devices, and the useful techniques to improve SOA of power MOSFETs for using in high-voltage integrated circuits are overviewed.
Circuit and Layout Co-Design for ESD Protection in Bipolar-CMOS-DMOS (BCD) High-Voltage Process
(2010-05-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The n-channel lateral double-diffused metal-oxide-semiconductor (nLDMOS) devices in high-voltage (HV) technologies are known to have poor electrostatic discharge (ESD) robustness. To improve the ESD robustness of nLDMOS, a co-design method combining a new waffle layout structure and a trigger circuit is proposed to fulfill the body current injection technique in this work. The proposed layout and circuit co-design method on HV nLDMOS has successfully been verified in a 0.5-mu m 16-V bipolar-CMOS-DMOS (BCD) process and a 0.35-mu m 24-V BCD process without using additional process modification. Experimental results through transmission line pulse measurement and failure analyses have shown that the proposed body current injection technique can significantly improve the ESD robustness of HV nLDMOS.
Design on power-rail ESD clamp circuit for 3.3-V I/O interface by using only 1-V/2.5-V low-voltage devices in a 130-nm CMOS process
(2006-10-01)
Ker, Ming-Dou
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Chen, Wen-Yi
;
Hsu, Kuo-Chun
;
電機學院
;
College of Electrical and Computer Engineering
A new power-rail electrostatic discharge (ESD) clamp circuit for application in 3.3-V mixed-voltage input-output (I/O) interface is proposed and verified in a 130-nm 1-V/2.5-V CMOS process. The devices in this power-rail ESD clamp circuit are all 1-V or 2.5-V low-voltage nMOS/pMOS devices, which are specially designed without suffering the gate-oxide reliability issue under 3.3-V I/O interface applications. A special ESD detection circuit realized with the low-voltage devices is designed and added in the power-rail ESD clamp circuit to improve ESD robustness of ESD clamp devices by substrate-triggered technique. The experimental results verified in a 130-nm CMOS process have proven the excellent effectiveness of this new proposed power-rail ESD clamp circuit.
Diode-Triggered Silicon-Controlled Rectifier With Reduced Voltage Overshoot for CDM ESD Protection
(2012-03-01)
Chen, Wen-Yi
;
Rosenbaum, Elyse
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Diode-triggered silicon-controlled rectifiers(DTSCRs) are used for on-chip electrostatic discharge protection. The role of the trigger diode string in determining the transient voltage overshoot is investigated using a very fast transmission line pulse. A DTSCR containing only poly-bound trigger diodes has a voltage overshoot of just 1.5 V at 7 A, which is significantly less than what is found with STI-bound diodes. A DTSCR with only STI-bound trigger diodes has a lower leakage current. Therefore, DTSCRs with different trigger diode configurations may be suitable for different applications, e. g., high speed or low power.
Electrostatic Discharge Protection Design for High-Voltage Programming Pin in Fully-Silicided CMOS ICs
(2011-02-01)
Ker, Ming-Dou
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Chen, Wen-Yi
;
Shieh, Wuu-Trong
;
Wei, I-Ju
;
電機學院
For integrated circuits (ICs) with voltage programming pin (V(PP) pin), a voltage higher than the normal power supply voltage of internal circuits is applied on the V(PP) pin to program the read-only memory (ROM). Because of the high programming voltage, the ESD diode placed from I/O pad to V(DD) cannot be applied to such V(PP) pin. In this work, a new ESD protection design is proposed to improve ESD robustness of V(PP) pin with the consideration of the mistriggering issue when V(PP) programming voltage has a fast rise time. In collaboration with the N-well ballast layout, the new proposed ESD protection design implemented in an IC product has been verified in a fully-silicided CMOS process to successfully achieve a high human-body-model ESD protection level of 5 kV.
ESD Protection Circuit for High-Voltage CMOS ICs with Improved Immunity Against Transient-Induced Latchup
(2010)
Ker, Ming-Dou
;
Hsu, Che-Lun
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Chen, Wen-Yi
;
電機學院
;
College of Electrical and Computer Engineering
With high normal operating voltages, latchup is an important reliability issue for high-voltage (HV) ICs. Harsh operating environments further deteriorate the transient-induced latchup (TLU) immunity of HV ICs. High immunity against TLU has therefore become an important reliability factor of HV ESD protection circuits. In this work, a novel ESD protection circuit with HV silicon controlled rectifier as the main ESD protection element has been proposed. The new proposed ESD protection circuit has been verified in a 0.5-mu m 16-V Bipolar CMOS DMOS process. Experimental results showed that the new proposed ESD protection circuit has high TLU immunity of +220V/-295V and high human body model (machine model) ESD robustness of 4.5kV (500V) at the same time.
High-Voltage nLDMOS in Waffle-Layout Style With Body-Injected Technique for ESD Protection
(2009-04-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
電機學院
;
College of Electrical and Computer Engineering
Electrostatic-discharge robustness of n-channel lateral DMOS (nLDMOS) has been significantly Increased in this letter through the waffle-layout style with body-current Injection. This body-injected technique on high-voltage nLDMOS has been successfully verified in a 0.5-mu m 16-V bipolar CMOS DMOS process without additional process or mask modification. The TLP-measured results confirmed that the secondary breakdown current (I(t2)) of nLDMOS has a more than 2x increase by the body-current injection.
HIGH-VOLTAGE TOLERANT POWER-RAIL ESD CLAMP CIRCUIT
(2007-10-04)
Ker, Ming-Dou
;
Chen, Wen-Yi
A high-voltage tolerant power-rail ESD clamp circuit is proposed, in which circuit devices can safely operate under the high power supply voltage that is three times larger than their process limitation without gate-oxide reliability issue. Moreover, an ESD detection circuit is used to effectively improve the whole ESD protection function by substrate-triggered technique. Because only low voltage (1*VDD) devices are used to achieve the object of high voltage (3*VDD) tolerance, the proposed design provides a cost effective power-rail ESD protection solution to chips with mixed-voltage interfaces.
Improvement on ESD Robustness of Lateral DMOS in High-Voltage CMOS ICs by Body Current Injection
(2009)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
Jou, Yeh-Ning
;
Huang, Yeh-Jen
;
Lin, Geeng-Lih
With the waffle layout style, body-injected technique implemented by body current injection on n-channel lateral DMOS (nLDMOS) has been successfully verified in a 0.5-mu m 16-V BCD process. The TIP measured results confirmed that the secondary breakdown current (I(t2)) of waffle nLDMOS can be significantly increased by the body current injection with the corresponding trigger circuit design. The latchup immunity of power-rail ESD protection circuit can be further improved by the stacked configuration with multiple nLDMOS devices in HV ICs.
Improving Safe Operating Area of nLDMOS Array With Embedded Silicon Controlled Rectifier for ESD Protection in a 24-V BCD Process
(2011-09-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In high-voltage technologies, silicon-controlled rectifier (SCR) is usually embedded in output arrays to provide a robust and self-protected capability against electrostatic discharge (ESD). Although the embedded SCR has been proven as an excellent approach to increasing ESD robustness, mistriggering of the embedded SCR during normal circuit operating conditions can bring other application reliability concerns. In particular, the safe operating area (SOA) of output arrays due to SCR insertion has been seldom evaluated. In this paper, the impact of embedding SCR to the electrical SOA (eSOA) of an n-channel LDMOS (nLDMOS) array has been investigated in a 24-V bipolar CMOS-DMOS process. Experimental results showed that the nLDMOS array suffers substantial degradation on eSOA due to embedded SCR. Design approaches, including a new proposed poly-bending (PB) layout, were proposed and verified in this paper to widen the eSOA of the nLDMOS array with embedded SCR. Both the high ESD robustness and the improved SOA of circuit operation can be achieved by the new proposed PB layout in the nLDMOS array.
Investigation on the validity of holding voltage in high-voltage devices measured by transmission-line-pulsing (TLP)
(2008-07-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
Huang, Yeh-Jen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Latch-up is one of the most critical issues in high-voltage (HV) ICs due to the high power-supply voltages. Because the breakdown junction of an HV device is easily damaged by the huge power generated from a dc curve tracer, the device immunity against latch-up is often referred to the transmission-line-pulsing. (TLP)-measured holding voltage. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mu m 18-V bipolar CMOS DMOS process to evaluate the validity of latch-up susceptibility by referring to the holding voltage measured by 100- and 1000-ns TLP systems and curve tracer. Long-pulse TLP measurement reveals the self-heating effect and self-heating speed of the n-channel LDMOS. The self-heating effect results in the TLP system to overestimate the holding voltage of HV n-channel LDMOS. Transient latch-up test is further used to investigate the susceptibility of HV devices to latch-up issue in field applications. As a-result, to judge the latch-up susceptibility of HV devices by holding voltage measured from TLP is insufficient.
Measurement on Snapback Holding Voltage of High-Voltage LDMOS for Latch-up Consideration
(2008)
Chen, Wen-Yi
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Ker, Ming-Dou
;
Huang, Yeh-Jen
;
Jou, Yeh-Ning
;
Lin, Geeng-Lih
In high voltage (HV) ICs, the latch-up immunity of HV devices is often referred to the TLP-measured holding voltage because the huge power generated from DC curve tracer can easily damage HV device during measurement. An n-channel lateral DMOS (LDMOS) was fabricated in a 0.25-mu m 18-V bipolar CMOS DMOS (BCD) process to investigate the validity of TLP-measured snapback holding voltage to the device immunity against latch-up. Experimental results from curve tracer measurement and transient latch-up test show that 100-ns TLP underestimates the latch-up susceptibility of the 18-V LDMOS. By using the long-pulse TLP measurement, snapback holding voltage of the HV device has been found to degrade over time due to the self-heating effect. As a result, since the latch-up event is a reliability test with the time duration longer than millisecond, TLP measurement is not suitable for applying to investigate the snapback holding voltage of HV devices for latch-up.
New Ballasting Layout Schemes to Improve ESD Robustness of I/O Buffers in Fully Silicided CMOS Process
(2009-12-01)
Ker, Ming-Dou
;
Chen, Wen-Yi
;
Shieh, Wuu-Trong
;
Wei, I-Ju
;
電機學院
Silicidation has been reported to result in substantial negative impact on the electrostatic discharge (ESD) robustness of MOS field-effect transistors. Although silicide blocking (SB) is a useful method to alleviate ESD degradation from silicidation, it requires additional mask and process steps to somehow increase the fabrication cost. In this paper, two new ballasting layout schemes to effectively improve the ESD robustness of input/output (I/O) buffers with fully silicided NMOS and PMOS transistors have been proposed. Ballasting technique in layout is a cost-effective method to enhance the ESD robustness of fully silicided devices. Experimental results from real IC products have confirmed that the new ballasting layout schemes can successfully increase the HBM ESD robustness of fully silicided I/O buffers from the original 1.5 kV to over 6 kV without using the additional SB mask.
New Layout Arrangement to Improve ESD Robustness of Large-Array High-Voltage nLDMOS
(2010-02-01)
Chen, Wen-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In high-voltage applications, large-array n-channel lateral DMOS (LA-nLDMOS) is usually required to provide high driving capability. However, without following the foundry-suggested electrostatic discharge (ESD) design guidelines in order to reduce total layout area, LA-nLDMOS is easily damaged once the parasitic bipolar junction transistor is triggered under ESD stresses. Accordingly, the bipolar triggering of LA-nLDMOS usually limits the ESD robustness of LA-nLDMOS, particularly in the open-drain structure. In this letter, a new layout arrangement for LA-nLDMOS has been proposed to suppress the bipolar triggering under ESD stresses. Measurement results in a 0.5-mu m 16-V bipolar CMOS DMOS process have confirmed that the new proposed layout arrangement can successfully increase the human-body-model ESD level of the LA-nLDMOS with effective width of 3000 mu m from the original 0.75 kV up to 2.75 kV.
Novel epoxy nanocomposite of low D-k introduced fluorine-containing POSS structure
(2007-02-15)
Wang, Yen-Zen
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Chen, Wen-Yi
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Yang, Chao-Chen
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Lin, Chen-Lung
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Chang, Feng-Chih
A nanoporous additives, polyhedral oilgomeric silisesquioxane containing eight functional hexafluorine groups, octakis(dimethylsiloxyhexafluoropropyl ether)silsesquioxane (OF) has been synthesized and blended with the UV-cured epoxy resin. The OF containing (10%) epoxy has significantly lower dielectric constant (2.65) than the plain epoxy (3.71). The incorporation of fluorine containing additives is well-known to reduce dielectric constant due to lower its polarizability. In addition, the presence of the bulky POSS structure is able to create additional free space or pores and further reduces the dielectric constant of the epoxy matrix. (c) 2007 Wiley Periodicals, Inc.
Novel nanocomposite of epoxy resin by introduced reactive and nanoporous material
(2007-12-01)
Yang, Chao-Chen
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Chang, Feng-Chih
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Wang, Yen-Zen
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Chan, Chia-Ming
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Lin, Chen-Lung
A reactive and nanoporous particle (OG) was introduced to UV-cured epoxy resin to form great low D-k material for electronic industrial. We expected the porous cage of OG to decrease the dielectric constant of UV-cured epoxy resin and multiple reactive functional groups (oxirane ring) of OG reacted with photoinitiator to increase the curing density of UV-cured epoxy resin. The glass transition temperatures (T-g) of epoxy increases with the increase of the OG content up to 10 phr due to the increase of crosslinking density. Excessive aggregation at highest OG content of 15 phr results in the reduced crosslinking density and T-g. The char yield of the composite increases with increase of OG content because stable Si and SiO2 are formed after thermal decomposition. The presence of OG results in the higher porosity and thus the lower dielectric constant.
Preparation and Characterization of Epoxy/Polyhedral Oligomeric Silsesquioxane Hybrid Nanocomposites
(2009-10-01)
Huang, Jieh-Ming
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Huang, Hui-Ju
;
Wang, Yu-Xiang
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Chen, Wen-Yi
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Chang, Feng-Chih
We have prepared epoxy/polyhedral oligomeric silsesquioxane (POSS) nanocomposites by photopolymerization from octakis(glycidylsiloxy)octasilsesquioxane (OG) and diglycidyl ether of bisphenol A. We used nuclear magnetic resonance, Raman, and Fourier transform infrared spectroscopies to characterize the chemical structure of the synthetic OG. Differential scanning calorimetry and dynamic mechanical analysis (DMA) revealed that the nanocomposites possessed higher glass transition temperatures than that of the pristine epoxy resin. Furthermore, DMA indicated that all of the nanocomposites exhibited enhanced storage moduli in the rubbery state, a phenomenon that we ascribe to both the nano-reinforcement effect of the POSS cages and the additional degree of crosslinking that resulted from the reactions between the epoxy and OG units. Thermogravimetric analysis revealed that the thermal stability of the nanocomposites was better than that of the pristine epoxy. (C) 2009 Wiley Periodicals, Inc. J Polym Sci Part B: Polym Phys 47: 1927-1934, 2009
Preparation and characterization of high-durability zwitterionic crosslinked proton exchange membranes
(2010-10-15)
Ye, Yun-Sheng
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Chen, Wen-Yi
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Huang, Yao-Jheng
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Cheng, Ming-Yao
;
Yen, Ying-Chieh
The present present paper describes the development of a novel proton exchange membrane comprising a poly (styrene sulfonic acid-co-4-vinylpyridine) copolymer that was crosslinked with a haloalkyl crosslinker through the formation of ionic bonding linkages The nucleophilic substitution of these crosslinked membranes as well as a model reaction between pyridine and 1-bromobutane was confirmed by nuclear magnetic resonance (NMR) Tough and flexible membranes of a high mechanical strength were prepared. They demonstrated very elevated thermal, hydrolytic and oxidative stabilities as compared to other sulfonated polymers. The crosslinked membrane composed of zwitterionic molecules with a crosslinking fraction of 90.3, denoted SP-1, exhibited a proton conductivity of ca 7 1 x 10(-2) S cm(-1) at 30 degrees C under 90% relative humidity; a value comparable to that of Nafion 117 Moreover, the crosslinked SP-1 membrane possessed the highest selectivity for methanol fuel cells (3 38 x 10(5) S cm(-3) s), approximately five times that of Nafion 117. thus implying its potential for practical use in high-energy-density devices (C) 2010 Elsevier B.V All rights reserved.