Browsing by Author "Chen-Yi"

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Absolute time delay generating device
(2010-11-02)
Lee
;
Chen-Yi
;
Yu
;
Jui-Yuan
;
Yu
An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.
Algorithm for a memory-based Viterbi decoder
(2007-08-28)
Lee
;
Chen-Yi
;
Lin
;
Chien-Ching
;
Wu
A method of convolutional decoding with a memory-based Viterbi decoder employs the property of a trace-back path; that is, the similarity between two consecutive trace-back paths becomes higher as the data error rate goes down. Therefore, the method of the invention saves the previous trace-back path into a register, and as soon as the current trace-back path is found to be the same as the previous one, the demanded path is obtained. After that, the memory read operations will stop, thereby reducing the power consumption caused by memory read operations. Prior to path trace-back, the path prediction can be executed by utilizing the property that the minimum path metric and the path are consecutive. The invention reduces the number of memory access operations and power consumption by employing the mechanisms of path matching and path prediction.
Apparatus of multi-stage network for iterative decoding and method thereof
(2010-05-25)
Wong
;
Cheng-Chi
;
Lee
;
Yung-Yu
;
Lai
An apparatus and method of multi-stage network for iterative network are disclosed. The apparatus has M stages, and each stage uses N multiplexers to transmit N codeword partitions simultaneously. Every starting terminal, either the output port of memories, soft-in soft-out decoders, or multiplexers, has two paths to couple with two different multiplexers at next stage. One path connects the source to the first data port of one multiplexer; the other connects the source to the second data port of another multiplexer. The two multiplexers will be controlled with the same 1-bit signal, so each source has only one valid path to next stage. The invention can guarantee that the transmission of N data blocks is free from contention.
Crystal-less communications device and self-calibrated clock generation method
(2011-04-12)
Lee
;
Chen-Yi
;
Yu
;
Jui-Yuan
A communication device uses a local clock generator to regenerate the carrier frequency of the reference signal from a remote communication. In particular, a closed loop is used to self-calibrate the local pulse till the frequency is fixed to be within a fixed frequency margin. Once the local pulse is obtained, the demodulator will use the local pulse to demodulate the reference signal to generate the data signal.
Instruction pre-fetch amount control with reading amount register flag set based on pre-detection of conditional branch-select instruction
(2005-01-11)
Chen
;
Pao-Lung
;
Lee
;
Chen-Yi
An architecture of method for fetching microprocessor's instructions is provided to pre-fetch and pre-decode a next instruction. If the instruction pre-decoded is found a conditional branch instruction, an instruction reading-amount register is set for reading two instructions next to the current instruction in the program memory, or one is read instead if the next instruction is found an instruction other than the conditional branch one so as to waive reading of unnecessary program memory and thereby reduce power consumption.
Method and apparatus for switching data in communication system
(2010-05-25)
Lee
;
Chen-Yi
;
Liu
;
Chih-Hao
;
Lin
A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive source data possessing real coding dimension and covert it to converted data possessing tolerable coding dimension; judgment bit is set in the converted data to designate the data as source data or not. Later on, shift circuit is used to shift the converted data in certain amount so as to generate a shifted data; meanwhile, the lowest bit and highest bit of shifted data are used to start acquiring real coding dimension to be used respectively as a first data and a second data, or by changing the pattern of acquiring the first data, then the highest bit minus the real coding dimension bit as the starting bit of the first data, and acquiring the real coding dimension from the side of the lowest bit. Finally, a comparison and selection circuit is used to compare the corresponding judgment bit in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.
Method and apparatus for switching data in communication system
(2010-05-25)
Lee
;
Chen-Yi
;
Lu
;
Jr-Hau
;
Lin
A method and apparatus for switching data in communication system which comprises of mainly a conversion circuit to receive the source data possessing in a real coding dimension and covert it to converted the data possessing in a tolerable coding dimension; the judgment bits are set in the converted data to designate the data as source data or not. Later on, shifter circuit is used to shift the converted data in certain amount and generates a shifted data; meanwhile, the right side and left side of shifted data are used to start acquiring the real coding dimension to be used respectively as a first data and a second data. Finally, a comparison and selection circuit is used to compare the corresponding judgment bits in the first and the second data and to output an output data, wherein output data is source data with the above-mentioned amount of shift.
Method for calculating syndrome polynomial in decoding error correction codes
(2005-10-11)
Lee
;
Chen-Yi
;
Chang
;
Hsie-Chia
;
Lin
The present invention provides a method of calculating the syndrome polynomial in decoding error correction codes. From the relation between the syndromes and the coefficients of the error locator polynomial, the inference that the first t syndromes are zeros, then the next t syndromes are also zeros can be deduced, wherein t is the largest number of correctable errors. For all received codewords, the first t syndromes are calculated. Next, whether the first t syndromes are zeros is judged. If the first t syndromes are zeros, the computation is stopped; otherwise, the next t syndromes are calculated. Therefore, the present invention can judge whether the received codeword is erroneous with only a half of computation, hence effectively reducing the computation in practical operation and achieving the object of low power consumption.
Multi-mode multi-parallelism data exchange method and device thereof
(2010-05-18)
Liu
;
Chih-Hao
;
Lin
;
Chien-Ching
;
Lee
A multi-mode multi-parallelism data exchange method and the device thereof are proposed to apply to a check node operator or a bit node operator. The proposed method comprises the steps of: duplicating part or all of an original shift data as a duplicated shift data; combining the original shift data and the duplicated shift data to form a data block; and using a data block as the unit to shift this data block so as to conveniently retrieve shift data from the shifted data block. With a maximum z factor circuit and duplication of part of data, specifications of different shift sizes can be supported. The functions of shifters of several sizes can therefore be accomplished with the minimum complexity.
Phase frequency detector with a narrow control pulse
(2004-12-14)
Lee
;
Chen-Yi
;
Chen
;
Pao-Lung
A phase frequency detector with a narrow control pulse comprises mainly two substantially equivalent phase latches with a narrow control pulse, and a reset signal generating unit. Each phase latch of a narrow control pulse has a clock pulse input end and a signal output end. Both latches also are connected to the reset signal generating unit. The logic value of each signal output end is decided by which clock pulse input appears first. The reset signal generating unit decides whether or not to generate a reset signal according to the logic values of both signal output ends. The reset signal is then sent to both phase latches of a narrow control pulse, if generated. The present invention can be implemented by a simple circuit. Comparing with the RS NAND PFD or master-slave D PFD, the PFD of the invention has the advantages of faster speed, saving more power and smaller IC chip area. Comparing with dynamic PFD, because the PFD of the invention has a feedback circuit, the storage charges of internal nodes will not be lost due to the leakage current and therefore the working frequency range is wider.