Browsing by Author "Cheng, Chao-Ching"

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A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Chung, Cheng-Ting
;
Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
Characteristics of atomic-layer-deposited Al(2)O(3) high-k dielectric films grown on Ge substrates
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Liu, Jun-Cheng
;
Kei, Chi-Chung
This paper describes the structural and electrical properties of Al(2)O(3) thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300 degrees C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al(2)O(3) film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al(2)O(3) and interfacial GeO(2) appeared at temperatures above 200 degrees C, along with degradation of the GeO(2)/Ge interface. Accordingly, a relatively large gate leakage current (J(g)) and a high density of interfacial states D(it) (> 10(13) cm(-2) eV(-1)) were observed as a result of deterioration of the entire Al(2)O(3)/Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600 degrees C in a N(2) ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO(x) volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H(2)/N(2), 1:10) at low temperature (300 degrees C) improved the capacitance-voltage characteristics of the Pt/Al(2)O(3)/Ge structure, in terms of providing a lower value of D(it) (ca. 6 x 10(11) cm(-2) eV(-1)), a lower value of J(g), and a reduced hysteresis width.
Demonstration of 40-nm Channel Length Top-Gate p-MOSFET of WS2 Channel Directly Grown on SiOx/Si Substrates Using Area-Selective CVD Technology
(2019-12-01)
Chung, Yun-Yan
;
Lu, Kuan-Cheng
;
Cheng, Chao-Ching
;
Li, Ming-Yang
;
Lin, Chao-Ting
For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 10(6), a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL).
Effects of interfacial sulfidization and thermal annealing on the electrical properties of an atomic-layer-deposited Al(2)O(3) gate dielectric on GaAs substrate
(2008-04-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Yang, Chun-Hui
;
Chang, Ching-Chih
In this study we investigated the interfacial chemistry occurring between an atomic-layer-deposited Al(2)O(3) high-k film and a GaAs substrate and the impact of sulfidization and thermal annealing on the properties of the resultant capacitor. We observed that sulfide passivation of the Al(2)O(3)/GaAs structure improved the effect of Fermi level pinning on the electrical characteristics, thereby providing a higher oxide capacitance, smaller frequency dispersion, and reduced surface states, as well as decreased interfacial charge trapping and gate leakage currents. Photoemission analysis indicated that the (NH(4))(2)S-treated GaAs improved the quality of the as-deposited Al(2)O(3) thin film and preserved the stoichiometry of the dielectric during subsequent high-temperature annealing. This behavior was closely correlated to the diminution of GaAs native oxides and elemental arsenic defects and their unwanted diffusion. In addition, thermal processing under an O(2) atmosphere, relative to that under N(2), decreased the thickness of the Al(2)O(3) gate dielectric and relieved the gate leakage degradation induced by metallic arsenic; as a result, superior dielectric reliability was attained. We discuss the underlying thermochemical reactions that account for these experimental observations. (C) 2008 American Institute of Physics.
Effects of Minority-Carrier Response Behavior on Ge MOS Capacitor Characteristics: Experimental Measurements and Theoretical Simulations
(2009-05-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Ling, Yu-Ting
;
Chang, Ruey-Dar
In this paper, we present MEDICI simulations of the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance Grub and high-low transition frequency f(tran), to explore the differences in the minority-carrier response. The Arrhenius-dependent G(sub) characteristics revealed that a larger energy loss-by at least four orders of magnitude-occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of f(tran). We confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency C-V curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al(2)O(3)/Ge MOS capacitors were consistent with the values of G(sub) and f(tran) obtained from MEDICI predictions and theoretical calculations. In addition, upon increasing the inversion biases, we observed shifts in the G(sub/)f conductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. (2-4) x 10(15) cm(-3) exist in present-day low-doped Ge wafers.
Electrical and material characterization of atomic-layer-deposited Al(2)O(3) gate dielectric on ammonium sulfide treated GaAs substrates
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Chang, Ching-Chih
;
Kei, Chi-Chung
This paper has studied the electrical and interfacial properties of atomic-layerdeposited Al(2)O(3) thin film on ammonium-sulfide passivated GaAs. It was found that the Al(2)O(3) deposited at 300 degrees C relative to that at 100 degrees C showed the nearly four orders of magnitude reduction in gate leakage current at the capacitance-equivalent-thickness of 40 angstrom. The capacitance-voltage (C-V) characteristics displayed the higher oxide capacitance, reduced frequency dispersion and less charge trapping when GaAs receiving (NH(4))(2)S sulfide immersion; these improvements can be reasonably explained by the suppression of both native oxides and the resultant improved interface quality. Annealing as-deposited Al(2)O(3)/GaAs structures at high temperatures further reduces the Fermi level pinning effect on accumulation capacitance, however, causes an increase in C-V frequency dispersion and gate leakage current. We suggested that these phenomena are strongly associated to the amount of As-related defects resided at the dielectric/ substrate interface during thermal desorption.
Experimental Demonstration of (111)-Oriented GaAs Metal-Oxide-Semiconductor Field-Effect-Transistors with Hetero-Epitaxial Ge Source/Drain
(2014)
Han, Tsung-Yu
;
Luo, Guang-Li
;
Cheng, Chao-Ching
;
Ko, Chih-Hsin
;
Wann, Clement H.
We demonstrate source/drain (S/D) design for GaAs n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) by embedding Ge into recessed S/D region to eliminate the intrinsic issues of the low solid solubility of dopants and low density of states (DOS) in GaAs material. For achieving high quality S/D epitaxy, the effects of substrate orientation and surface preparation on the quality of the epitaxial Ge film were investigated. High quality Ge film was successfully grown on the GaAs (111)A substrate by using a ultra high vacuum chemical vapor deposition (UHVCVD) tool and the significant improvement in the surface root-mean-square (RMS) roughness was observed as compared to that on the (100) substrate. The fabricated GaAs NMOSFET with hetero-Ge S/D exhibits an I-on/I-off ratio of similar to 2.5 x 10(2). Even though the performance can be further improved, we think our proposed scheme sheds the light on overcoming the issues of the low solid solubility of n-dopant and low DOS in III-V MOSFETs. (C) 2014 The Electrochemical Society. All rights reserved.
First demonstration of 40-nm channel length top-gate WS2 pFET using channel area-selective CVD growth directly on SiOx/Si substrate
(2019-01-01)
Cheng, Chao-Ching
;
Chung, Yun-Yan
;
Li, Ming-Yang
;
Lin, Chao-Ting
;
Li, Chi-Feng
Area-selective channel material growth for 2D transistors is more desirable for volume manufacturing than exfoliation or wet/dry transfer after large area growth. We demonstrate the first top-gate WS(2)p-channel field-effect transistors (p-FETs) fabricated on SiOx/Si substrate using channel area-selective CVD growth. Smooth and uniform WS2 comprising approximately 6 layers was formed by area-selective CVD growth in which a patterned tungsten-source/drain served as the seed for WS2 growth. For a 40 nm gate length transistor, the device has impressive electrical characteristics: on/off ratio of similar to 10(6), a S.S. of similar to 97 mV/dec.. and nearly zero DIBL.
Five-element circuit model using linear-regression method to correct the admittance measurement of metal-oxide-semiconductor capacitor
(2009-01-01)
Cheng, Chao-Ching
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Chien, Chao-Hsin
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Luo, Guang-Li
;
Liu, Jun-Cheng
;
Chen, Yi-Cheng
The authors present a linear-regression method based on a five-element circuit model to correct measured capacitance-voltage and conductance-voltage curves. This model explains the effects of series resistance and parasitic capacitance/inductance on the frequency dispersion of measured capacitance and the magnification of measured conductance. These extracted parasitic components show significant dependencies on the geometry of capacitor structure, thereby causing different frequency-dependent capacitance characteristics in measurements. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3058724]
Ge Epitaxial Growth on GaAs Substrates for Application to Ge-Source/Drain GaAs MOSFETs
(2010)
Luo, Guang-Li
;
Han, Zong-You
;
Chien, Chao-Hsin
;
Ko, Chih-Hsin
;
Wann, Clement H.
Ge films were epitaxially grown on GaAs(100) substrates and Ga(0.88)In(0.12)As(100) virtual substrates using an ultrahigh vacuum/chemical vapor deposition system. The incubation time of Ge growth depends on Ga(In)As surfaces that were processed by different wet chemical solutions. Growth behaviors, such as island growth at the initial stages and selective growth into recessed regions of GaAs, were studied by transmission electron microscopy. To test the quality of Ge grown on GaAs, an n(+)-Ge/p-GaAs diode was fabricated. We propose that through Ge selective epitaxial growth, Ge can be used as the source-drain of a GaAs metal-oxide-semiconductor field-effect transistor (MOSFET) to overcome some intrinsic limitations of this device. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3246000] All rights reserved.
High-speed GaAs metal gate semiconductor field effect transistor structure grown on a composite Ge/Ge(x)Si(1-x)/Si substrate
(2007-04-15)
Luo, Guang-Li
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Hsieh, Yen-Chang
;
Chang, Edward Yi
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Pilkuhn, M. H.
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Chien, Chao-Hsin
In this study we used a low-pressure metal organic vapor phase epitaxy method to investigate the growth of GaAs metal gate semiconductor field effect transistor (MESFET) structures on a Si substrate. The buffer layer between the Si substrate and the grown GaAs epitaxial layers was a composite Ge/Si(0.05)Ge(0.95)/Si(0.1)Ge(0.9) metamorphic layer. We used transmission electron microscopy to observe the microstructures formed in the grown GaAs/Ge/Si(x)Ge(1-x)/Si material and atomic force microscopy to analyze the surface morphology and the formation of antiphase domains in the GaAs epitaxial layers. The measured Hall electron mobility in the channel layer of a MESFET structure grown on a 6 degrees misoriented Si substrate was 2015 cm(2) V(-1) s(-1) with a carrier concentration of 5.0x10(17) cm(-3). The MESFET device fabricated on this sample exhibited good current-voltage characteristics.
III-V MOSFETs with a New Self-Aligned Contact
(2010)
Zhang, Xingui
;
Guo, Huaxin
;
Ko, Chih-Hsin
;
Wann, Clement H.
;
Cheng, Chao-Ching
We report the first demonstration of III-V n-MOSFETs with self-aligned contact technology. The self-aligned contact was formed using a salicide-like process which is compatible with CMOS process flow. A new epitaxy process was developed to selectively form a thin continuous germanium-silicon (GeSi) layer on gallium arsenide (GaAs) source and drain (S/D) regions. Nickel was deposited and annealed to form NiGeSi, and unreacted metal was removed. A second anneal diffuses Ge and Si into GaAs to form heavily n+ doped regions, and a novel self-aligned nickel germanosilicide (NiGeSi) ohmic contact was achieved. MOSFETs with the new self-aligned metallization process were realized.
Improved electrical properties of Gd2O3/GaAs capacitor with modified wet-chemical clean and sulfidization procedures
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Tseng, Chih-Kuo
;
Chiang, Hsin-Che
In this study we demonstrated improved electrical characteristics of Gd2O3 dielectric thin films on n-GaAs substrate by manipulating wet-chemical clean and (NH4)(2)S passivation. With X-ray photoelectron spectroscopy analysis, the HCl-cleaned GaAs surface was characterized to possess oxide species mainly in the form of AS(2)O(x) near the outmost surface and Ga2Ox with elemental arsenic close to the interface. These undesirable components could be suppressed through rinsing in NH4OH alkaline solution and then performing sulfidization at 80 degrees C, resulting in alleviating the Fermi level pinning effect on Gd2O3/GaAs capacitor performance. Higher oxide capacitance and alleviated frequency dispersion at the accumulation/depletion regimes were achieved, accompanied by negligible charge trapping (< 100 mV). Accordingly, gate leakage J(g) was lowered to ca. 10(-5) A/cm(2) at gate voltage V-g = (V-FB + 1) V, which was comparable to the recently reported performance of HfO2/GaAs structure with an ultrathin Si/Ge interfacial layer. We attributed the electrical improvements to the enhanced stabilization of high-k/sulfur-terminated GaAs interface due to abatement of native oxides and excess arsenic segregation. (C) 2007 The Electrochemical Society.
Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al(2)O(3) Gate Dielectric
(2009-08-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Lin, Ching-Lun
;
Chen, Hung-Sen
In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-Al(2)O(3) gate dielectrics. The magnitudes of the rectifying ratios for the Ge p(+)-n and n(+)-p junctions exceeded three and four orders of magnitude (in the voltage range of +/-1 V), respectively, with accompanying reverse leakages of ca. 10(-2) and 10(-4) A . cm(-2), respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 degrees C boosted the device on-current, decreased the Al(2)O(3)/Ge interface states to 8 x 10(11) cm(-2) . eV(-1), and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm(2) . V(-1) . s(-1) and > 10(3), respectively, for the p-FET (W/L = 100 mu m/4 mu m), while these values were less than 100 cm(2) . V(-1) . s(-1) and ca. 10(3), respectively, for the n-FET (W/L = 100 mu m/9 mu m). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.
Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al2O3 Gate Dielectric
(2009-08-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Lin, Ching-Lun
;
Chen, Hung-Sen
In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p(+)-n and n(+)-p junctions exceeded three and four orders of magnitude (in the voltage range of +/-1 V), respectively, with accompanying reverse leakages of ca. 10(-2) and 10(-4) A . cm(-2), respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 degrees C boosted the device on-current, decreased the Al2O3/Ge interface states to 8 x 10(11) cm(-2) . eV(-1), and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm(2) . V-1 . s(-1) and > 10(3), respectively, for the p-FET (W/L = 100 mu m/4 mu m), while these values were less than 100 cm(2) . V-1 . s(-1) and ca. 10(3), respectively, for the n-FET (W/L = 100 mu m/9 mu m). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.
Nearly Dislocation-free Ge/Si Heterostructures by Using Nanoscale Epitaxial Growth Method
(2012-01-01)
Luo, Guang-Li
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Ko, Chih-Hsin
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Wann, Clement H.
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Chung, Cheng-Ting
;
Han, Zong-You
The selective growth of germanium into nanoscale trenches on silicon substrates was investigated. These nanoscale trenches-the smallest size of which was 50 nm-were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. It was found that the formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. It was considered that for the Ge grown in nanoscale Si areas (e. g., several tens of nanometers), the TDs were readily removed during cyclic thermal annealing, predominantly because their gliding distance to the SiO2 sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density. (C) 2011 Published by Elsevier B.V. Selection and/or peer-review under responsibility of Garry Lee
Self-aligned contact metallization technology for III-V metal-oxide-semiconductor field effect transistors
(2011-05-01)
Zhang, Xingui
;
Guo, Huaxin
;
Lin, Hau-Yu
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Cheng, Chao-Ching
;
Ko, Chih-Hsin
The demonstration of a salicidelike self-aligned contact technology for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is reported. A thin and continuous crystalline germanium-silicon (GeSi) layer was selectively formed on n(+) doped gallium arsenide (GaAs) regions by epitaxy. A new self-aligned nickel germanosilicide (NiGeSi) Ohmic contact with good morphology was achieved using a two-step annealing process with precise conversion of the GeSi layer into NiGeSi. NiGeSi contact with the contact resistivity (rho(c)) of 1.57 Omega mm and sheet resistance (R(sh)) of 2.8 Omega/square was achieved. The NiGeSi-based self-aligned contact technology is promising for future integration in high performance III-V MOSFETs. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3592211]
Study of thermal stability of HfOxNy/Ge capacitors using postdeposition annealing and NH3 plasma pretreatment
(2007)
Cheng, Chao-Ching
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Chien, Chao-Hsin
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Luo, Guang-Li
;
Yang, Chun-Hui
;
Kuo, Mei-Ling
We studied the thermal stability of the as-deposited HfOxNy thin films on the Ge substrate by employing rapid thermal annealing. After undergoing high-temperature processing, we observed several interesting physical and electrical features presented in the HfOxNy/Ge system, including a large Ge out-diffusion (>15 atom %) into high-k films, positive shift of the flatband voltage, severe charge trapping, and increased leakage current. These phenomena are closely related to the existence of GeOx defective layer and the degree of resultant GeO volatilization. We abated these undesirable effects, especially for reducing the amount of Ge incorporation (< 5 atom %) and the substoichiometric oxide at dielectric-substrate interface, through performing NH3 plasma pretreatment on the Ge surface. These improvements can be interpreted in terms of a surface nitridation process that enhanced the thermal stability of the high-k/Ge interface. In addition, we measured that the conductance loss in inversion was still high and it revealed independence with respect to gate bias, reflecting the fact that the minority carriers in Ge can rapidly respond either through a diffusion mechanism or through midgap trap states residing in Ge bulk substrates. (C) 2007 The Electrochemical Society.
The Annihilation of Threading Dislocations in the Germanium Epitaxially Grown within the Silicon Nanoscale Trenches
(2009)
Luo, Guang-Li
;
Huang, Shih-Chiang
;
Ko, Chih-Hsin
;
Wann, Clement H.
;
Chung, Cheng-Ting
We investigated the selective growth of germanium into nanoscale trenches on silicon substrates. These nanoscale trenches, the smallest size of which was 50 nm, were fabricated using the state-of-the-art shallow trench isolation technique. The quality of the Ge films was evaluated using transmission electron microscopy. The formation of threading dislocations (TDs) was effectively suppressed when using this deposition technique. For the Ge grown in nanoscale Si areas (e.g., several tens of nanometers), the TDs were probably readily removed during cyclic thermal annealing predominantly because their gliding distance to the SiO(2) sidewalls was very short. Therefore, nanoscale epitaxial growth technology can be used to deposit Ge films on lattice-mismatched Si substrates with a reduced defect density.
Thermochemical reaction of ZrOx(N-y) interfaces on Ge and Si substrates
(2006-07-03)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Lin, Je-Hung
;
Chang, Chun-Yen
;
Luo, Guang-Li
We have studied the thermochemical characteristics of ZrOx(N-y)/Ge and Si interfaces by employing postdeposition annealing. We found that Ge oxide species severely desorbed from the inherent interfacial layer, which was speculated to retard the formation of Zr germanate during high-temperature processing. These unique features enable ZrOx(N-y)/Ge gate stack to show a better equivalent-oxide-thickness scalability as compared to ZrOx(N-y)/Si gate stack. However, the volatilization of GeOx-contained interfacial layer also caused the formation of small pits and/or holes in the overlying ZrOx(N-y) gate dielectrics, which was expected to cause deterioration in the electrical properties of fabricated high-k/Ge devices. (c) 2006 American Institute of Physics.