Browsing by Author "Chin, Albert"

Now showing 1 - 20 of 169

A 2.4 GHz CMOS Power Amplifier Using Asymmetric MOSFETs
(2012)
Liu, Szu-Ling
;
Huang, Yu-Chien
;
Chen, Ying-Jen
;
Chang, Tsu
;
Chin, Albert
In this paper, a two-stage 2.4 GHz power amplifier (PA) using the high-breakdown-voltage asymmetric NMOSFETs was implemented in a 0.18-mu m CMOS technology. In this process, the conventional NMOSFETs have a drain-to-source breakdown voltage (BVdss) about 3.5V, therefore restricting the available output power in PA designs. However, by using the special asymmetric NMOSFETs in the proposed PA, the circuit can safely operate at a supply voltage from 1.8 to 2.75V. Under a 2.75V operation, good power performances include a power gain of 20.4 dB, an output 1-dB compression point (P-out,P-1dB) of 21.5dBm and a power-added-efficiency (PAE) of 29.6%.
A 2.4/5 GHz dual-band VCO using a variable inductor and switched resonator
(2007)
Kao, H. L.
;
Yang, D. Y.
;
Chin, Albert
;
McAlister, S. P.
;
電機學院
A dual-band, low phase noise, low power and small sized voltage-controlled oscillator (VCO) with a variable inductor and switched resonator is described. The dual-band VCO operated near 2.4 GHz and 5 GHz with a phase noise of 120 and -121 dBc/Hz at a 1 MHz offset and a tuning range of 250 MHz and 1.2 GHz, respectively. The power consumption was 1.5/1.8 mW for 2.4/5 GHz operations. The total size the VCO was only 1.06 mm(2), which was achieved by using one inductor which was connected with a switch to give good dual-band operation and performance.
A Bias-Varied Low-Power K-band VCO in 90 nm CMOS Technology
(2012-06-01)
Liu, Szu-Ling
;
Tian, Xin-Cheng
;
Hao, Yue
;
Chin, Albert
;
電子工程學系及電子研究所
This letter presents a novel bias-varied low-power K-band voltage controlled oscillator (VCO) in a standard 90 nm CMOS technology. This circuit exhibits low power consumption of <= 3mW and a 12.2% tuning range with low phase noise characteristic. These performances are realized by combination of the transformer-feedback and the switchable active circuit block, which can control the dc power at different frequencies and improve the phase noise.
A CMOS-Compatible, High RF Power, Asymmetric-LDD MOSFET with Excellent Linearity
(2008)
Chang, T.
;
Kao, H. L.
;
Chen, Y. J.
;
Liu, S. L.
;
McAlister, S. P.
We report the performance of 0.18 mu m RF power MOSFETs with an Asymmetric-Lightly-Doped-Drain (LDD) design. Such devices do not have an n-type drain extension and exhibited better characteristics than conventional MOSFETs at same gate length. The devices showed a DC breakdown voltage of 6.9 V, a 0.54 W/mm power density, 115 GHz f(max), and a good adjacent channel power ratio (ACPR) linearity, as well as a 52% drain efficiency at 2.4 GHz.
A Dual-Resonant Mode 10/22-GHz VCO With a Novel Inductive Switching Approach
(2012-07-01)
Liu, Szu-Ling
;
Chen, Kuan-Han
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a novel dual-band voltage-controlled oscillator (VCO) in a standard 0.18-mu m CMOS technology. With special design in the LC tank, the circuit exhibits two oscillation modes in different frequency bands. The frequency band selection is achieved by a switched coupled inductor with the tunable inductance and quality factor. This VCO can operate in a 10-GHz band with 7.6% tuning range and a 22-GHz band with 8% tuning range, while the core circuit draws a dc current of 8.44 mA from a 1.8-V supply voltage. The figures-of-merit at 10- and 22-GHz bands are -184.63 and -181.81 dBc/Hz, respectively. These performances are comparable with state-of-the-art dual-band LC-VCOs.
A flexible organic pentacene nonvolatile memory based on high-kappa dielectric layers
(2008-12-08)
Chang, Ming-Feng
;
Lee, Po-Tsung
;
McAlister, S. P.
;
Chin, Albert
;
電子工程學系及電子研究所
We report a pentacene thin film transistor nonvolatile memory fabricated on a flexible polyimide substrate. This device shows a low program/erase voltage of 12 V, a speed of 1/100 ms, an initial memory window of 2.4 V, and a 0.78 V memory window after 48 h. This has been achieved by using a high-kappa dielectric as charge trapping, blocking, and tunneling gate insulator layers.
A Low Operating Voltage IGZO TFT Using LaLuO3 Gate Dielectric
(2013)
Chou, Kun-I
;
Hsu, Hsiao-Hsuan
;
Cheng, Chun-Hu
;
Lee, Kai-Yu
;
Li, Shang-Rong
This study proposes a low operation voltage indium-gallium-zinc oxide (IGZO) thin-film transistor using a high-kappa lanthanum-lutetium oxide as the gate dielectric. It is the first time to integrate the high-kappa LaLuO3 into an IGZO TFT. The resulting LaLuO3/IGZO TFT shows a low threshold voltage of 0.32 V, a small sub-threshold swing of 310 mV/decade and an acceptable mobility (mu(FE)) of 6.6 cm(2)/V-s. The low V-T and small SS allow device operation voltage below 2.5 V.
A Low Operating Voltage ZnO Thin Film Transistor Using a High-kappa HfLaO Gate Dielectric
(2010)
Su, N. C.
;
Wang, S. J.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This study demonstrates the feasibility of producing a ZnO thin film transistor (TFT) using hafnium-lanthanum-oxide (HfLaO) as the gate dielectric. By integrating high-kappa HfLaO with an amorphous ZnO channel, the resulting HfLaO/ZnO TFTs display a low threshold voltage (V(T)) of 0.28 V, a small subthreshold swing (SS) of 0.26 V/dec, an acceptable mobility (mu(sat)) of 3.5 cm(2)/V s, and a good I(on)/I(off) ratio of 1 X 10(6). The SS heavily depends on the HfLaO/ZnO interface charges, a property which is related to the degree of crystallization of ZnO. The low VT and the small SS allow device voltage operation below 2 V for low power application. (C) 2009 The Electrochemical Society. [DOI: 10.1149/1.3257607] All rights reserved.
A low-power current-reuse LNA for ultra-wideband wireless receivers from 3.1 to 10.6 GHz
(2007)
Kao, H. L.
;
Chin, Albert
;
Chang, K. C.
;
McAlister, S. P.
;
交大名義發表
We present an ultra-wideband 3.1-10.6 GHz low-noise amplifier which uses a two-stage current-reuse structure to reduce the power. Fabricated in a 0.18 mu m CMOS process, the IC prototype achieved a power gain of 9.3 dB, a noise figure (NF) of < 5.6 dB, an input match of < -8 dB over the band, while consuming only 9.4 mW.
A Low-Power K-Band CMOS VCO With Four-Coil Transformer Feedback
(2010-08-01)
Liu, Szu-Ling
;
Chen, Kuan-Han
;
Chang, Tsu
;
Chin, Albert
;
電子工程學系及電子研究所
A K-band low-power and low-phase-noise voltagec-ontrolled oscillator (VCO) is presented in this letter. By utilizing four-coil transformer feedback and forward body bias topology, good performances are obtained under a low-power supply with a 5.1% tuning range and a phase noise of -109.8 dBc/Hz at 1 MHz offset from the 21.37-GHz carrier frequency. The core circuit of this VCO only consumes 3.5 mW with a 0.6-V supply voltage and a 0.55-V body bias.
A Nonvolatile InGaZnO Charge-Trapping-Engineered Flash Memory With Good Retention Characteristics
(2010-03-01)
Su, Nai-Chao
;
Wang, Shui Jinn
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We report an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor nonvolatile memory (NVM). This NVM shows a large 1.2-V extrapolated ten-year memory window, along with low 10-V/-12-V program/erase voltage, fast 1-ms/100-mu s speed, and good endurance. This was achieved using a charge-trap-engineered structure and high-kappa layers.
A Novel Read Scheme for Large Size One-Resistor Resistive Random Access Memory Array
(2017-02-10)
Zackriya, Mohammed, V
;
Kittur, Harish M.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The major issue of RRAM is the uneven sneak path that limits the array size. For the first time record large One-Resistor (1R) RRAM array of 128x128 is realized, and the array cells at the worst case still have good Low-/High-Resistive State (LRS/HRS) current difference of 378 nA/16 nA, even without using the selector device. This array has extremely low read current of 9.7 mu A due to both low-current RRAM device and circuit interaction, where a novel and simple scheme of a reference point by half selected cell and a differential amplifier (DA) were implemented in the circuit design.
A parallel coupled-line filter using VLSI backend interconnect with high resistivity substrate
(2006-01-01)
Chen, C. C.
;
Kao, H. L.
;
Chiang, K. C.
;
Chin, Albert
;
電子工程學系及電子研究所
This paper reports our progress in developing parallel coupled-line filters based on Si-based VLSI backend interconnects for millimeter-wave applications. The resonant frequency of this coupled-line filter increases with increasing spacing-gap and with increasing IDM thickness. By using high resistivity substrate, the parallel coupled-line band-pass filter is extremely effective in reducing substrate loss, and also provides very low insertion loss, even at the millimeter-wave regime. In addition, the parallel coupled-line filter suitable for advanced system-on-a-chips at the millimeter wave application achieves high performance characteristics, which show low insertion loss, wide band, and compatibility with standard VLSI process.
A program-erasable high-k Hf0.3N0.2O0.5 MIS capacitor with good retention
(2007-10-01)
Yang, H. J.
;
Chin, Albert
;
Chen, W. J.
;
Cheng, C. F.
;
Huang, W. L.
We describe a programmable-erasable MIS capacitor with a single high-kappa Hf0.3N0.2O0.5 dielectric layer. This device showed a capacitance density of similar to 6.6 fF/mu m(2), low program and erase voltages of +5 and -5 V, respectively, and a large Delta V-fb memory window of 1.5 V. In addition, the 25 degrees C data retention was good, as indicated by program and erase decay rates of only 2 and 6.2 mV/dec, respectively. Such device retention is attributed to the deep trapping level of 1.05 eV in the Hf0.3N0.2O0.5.
A Study on Frequency-Dependent Voltage Nonlinearity of SrTiO(3) rf Capacitor
(2010-01-01)
Cheng, C. H.
;
Huang, C. C.
;
Hsu, H. H.
;
Chen, P. C.
;
Chiang, K. C.
In this article, we investigate the frequency-dependent voltage nonlinearity effect of high-kappa Ni/SrTiO(3)/TaN and TaN/SrTiO(3)/TaN radio-frequency (rf) metal-insulator-metal (MIM) capacitors by electrical and thermal stresses. The experimental results demonstrated that the MIM-related capacitance properties, dependence of voltage and frequency, are not only affected by intrinsic dielectric properties but also shared by extrinsic effect, which possibly originated from the oxygen vacancies or electrode polarization. The high work-function Ni electrode can prevent the frequency-dependent voltage coefficient of capacitance characteristics from deterioration under the high temperature or continued voltage-stressing environments. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3491490] All rights reserved.
A Study on Frequency-Dependent Voltage Nonlinearity of SrTiO3 rf Capacitor
(2010-01-01)
Cheng, C. H.
;
Huang, C. C.
;
Hsu, H. H.
;
Chen, P. C.
;
Chiang, K. C.
In this article, we investigate the frequency-dependent voltage nonlinearity effect of high-kappa Ni/SrTiO3/TaN and TaN/SrTiO3/TaN radio-frequency (rf) metal-insulator-metal (MIM) capacitors by electrical and thermal stresses. The experimental results demonstrated that the MIM-related capacitance properties, dependence of voltage and frequency, are not only affected by intrinsic dielectric properties but also shared by extrinsic effect, which possibly originated from the oxygen vacancies or electrode polarization. The high work-function Ni electrode can prevent the frequency-dependent voltage coefficient of capacitance characteristics from deterioration under the high temperature or continued voltage-stressing environments. (C) 2010 The Electrochemical Society. [DOI: 10.1149/1.3491490] All rights reserved.
Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack
(2013-04-01)
Cheng, C. H.
;
Chou, K. I.
;
Chin, Albert
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V-t) of 0.31 V. This small EOT MOSFET was achieved by employing high-kappa CeO2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-kappa SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node. (C) 2013 Elsevier Ltd. All rights reserved.
Advance in next Century nanoCMOSFET research
(2007-10-31)
Hwang, Huey-Liang
;
Chiou, Yan-Kai
;
Chang, Che-Hao
;
Wang, Chen-Chan
;
Lee, Kun-Yu
It is well known that Taiwan's IC industry is in the very leading front of the world, and production of 65 nm devices was launched in 2006. Within a few years, the need of high-k dielectrics and metal gates is eminent and truly indispensable. Professor H.L. Hwang (the author) organized 12 professors and 50 graduate students of National Tsing Hua University and Chiao Tung University, and executed this particular project, which is sponsored by the Ministry of Economic Affairs of Republic of China, and is aimed at treating efficiently this problem and transferred the critical technologies to industry in a time frame of 3 years. (C) 2007 Elsevier B.V. All rights reserved.
Advanced Metal-Gate/High-kappa CMOS with Small EOT and Better High Field Mobility
(2012)
Chin, Albert
;
Chen, W. B.
;
Chen, P. C.
;
Wu, Y. H.
;
Chi, C. C.
Continuously down-scaling the operation voltage, saving energy, and maintaining high performance are the major challenge for CMOS device. Small 0.95 similar to 1.4 nm equivalent-oxide thickness (EOT) and 1.4 similar to 2.5X better mobility than universal SiO2/Si data are achieved in metal-gate/high-kappa/Ge CMOS at 1 MV/cm effective field (E-eff). These excellent performances were achieved by using interface engineering and novel process, to overcome the poor high-kappa/Ge interface reaction, low source-drain dopant activation, and n(+)/p ohmic contact. The all-Ge CMOS with measured higher electron and hole mobility has irreplaceable merits of much simpler process, lower cost, and potentially higher yield than the InGaAs-nMOS/Ge-pMOS platform for IC manufacture.
All Nonmetal Resistive Random Access Memory
(2019-04-16)
Yen, Te Jui
;
Gismatulin, Andrei
;
Volodin, Vladimir
;
Gritsenko, Vladimir
;
Chin, Albert
Traditional Resistive Random Access Memory (RRAM) is a metal-insulator-metal (MIM) structure, in which metal oxide is usually used as an insulator. The charge transport mechanism of traditional RRAM is attributed to a metallic filament inside the RRAM. In this paper, we demonstrated a novel RRAM device with no metal inside. The N+-Si/SiOx/P+-Si combination forms a N+IP+ diode structure that is different from traditional MIM RRAM. A large high-resistance/low-resistance window of 1.9 x 10(4) was measured at room temperature. A favorable retention memory window of 1.2 x 10(3) was attained for 10(4)s at 85 degrees C. The charge transport mechanism of virgin, high- and low-resistance states can be well modeled by the single Shklovskii-Efros percolation mechanism rather than the charge transport in metallic filament. X-ray photoelectron spectroscopy demonstrated that the value of x in SiOx was 0.62, which provided sufficient oxygen vacancies for set/reset RRAM functions.