Browsing by Author "Chiu, Chia-Sung"

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A Miniature 92-95 GHz On-chip Slow-wave Branch-line Coupler
(2018-01-01)
Chen, Yi-Tang
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Chiu, Chia-Sung
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Chuang, Chia-Wei
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Chen, Kun-Ming
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Huang, Guo-Wei
A miniature 92-95 GHz on-chip branch-line coupler (BLC) employing a slow-wave microstrip line is proposed herein. The ground metal plane beneath the signal line is periodically slotted, and the coupler can be highly miniaturized owing to the short wavelength characteristic of the transmission line with slow-wave structure. The size of the slow-wave BLC is 250 mu m X 250 mu m, which is 39% of the size of conventional BLCs.
Analog and RF Characteristics of Power FinFET Transistors With Different Drain-Extension Designs
(2018-10-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chen, Hsiu-Chih
Analog and RF characteristics of power FinFET transistors with different drain-extension structures are investigated for microwave integrated circuit applications. The power FinFETs were designed based on the drain-extended MOSFET structure and fabricated using a standard low-voltage FinFET process. Three various drain-extension configurations are demonstrated and compared. With the low-doped drain extension, the breakdown voltage of power FinFETs is higher than 6.5 V for all samples. For standard power devices, where the drain extension is performed with narrow fins, a high drain resistance is inevitable, resulting in high on-resistance and poor analog and RF performances. For devices with wide drain-extension fins (wide drain FinFET) or a planar drain extension (hybrid FinFET), lower drain resistances are obtained owing to the larger extension width. Therefore, the on-resistances of the wide drain and hybrid devices are much lower than that of the standard counterpart. Moreover, these devices with modified drain extensions also exhibit better analog and RF behaviors. The cutoff frequency of power FinFETs is boosted from 30 to 53 GHz when the drain extension is changed from narrow fins to a planar layout. These experimental results indicate that RF power FinFETs with good performance would be realized with the modified drain-extension designs.
Capacitance Characteristics Improvement and Power Enhancement for RF LDMOS Transistors Using Annular Layout Structure
(2011-03-01)
Chiu, Chia-Sung
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Chen, Kun-Ming
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Huang, Guo-Wei
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Chen, Ming-I.
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Yang, Yu-Chi
This paper presents an annular-structure lateral-diffused metal-oxide-semiconductor (LDMOS) RF transistor using a 0.5-mu m LDMOS process. This paper also examines the dc, small-signal, and large-signal characteristics of RF LDMOS transistors with different closed structures. In particular, the problem of evaluating the LDMOS aspect ratio for annular structure is addressed. The capacitance characteristics improvement in the LDMOS device design using the annular structure was also investigated. The power gain and efficiency of annular structure give nearly 5% enhancement compared to the traditional structure with 80-mu m gatewidth at 1.9 GHz. Results show that the annular structure appears to be a better layout design for RF LDMOS transistors.
Characterization of Annular-Structure RF LDMOS Transistors Using Polyharmonic Distortion Model
(2009)
Chiu, Chia-Sung
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Chen, Kun-Ming
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Huang, Guo-Wei
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Hsiao, Chih-Hua
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Liao, Kuo-Hsiang
An annular-structure lateral-diffused metal-oxide semiconductor (LDMOS) RF transistor with polyharmonic distortion (PHD) model characterized by nonlinear vector network analyzer is described in this paper. The devices were fabricated using a 0.5 mu m LDMOS process. The DC, small-signal, and large-signal characteristics of RF LDMOS transistors with annular-structures were also studied in this work. Using the PHD model, the accuracy of intermodulation and time waveform is verified. Furthermore, the model via X-parameter shows good agreement without optimization.
High-frequency performances of superjunction laterally diffused metal-oxide-semiconductor transistors for RF power applications
(2016-04)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chang, Edward Yi
This paper presents the dc and high-frequency performances of laterally diffused metal-oxide-semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-mu m CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers. (C) 2016 The Japan Society of Applied Physics
High-frequency performances of superjunction laterally diffused metal-oxide-semiconductor transistors for RF power applications
(2016-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chang, Edward Yi
This paper presents the dc and high-frequency performances of laterally diffused metal-oxide-semiconductor (LDMOS) transistors with superjunction (SJ) structures. The SJ-LDMOS transistors were fabricated using a 0.5-mu m CMOS process. By utilizing a modified SJ/RESURF layout (Type I) or a tapered SJ layout (Type II) in our devices, better high-frequency performances and higher breakdown voltages are achieved compared with conventional SJ counterpart, owing to the suppression of the substrate-assisted depletion effect and the reduction of the drain resistance. For Type I device with an optimal SJ layout dimension, the cutoff frequency and the breakdown voltage are 3.7 GHz and 68 V, respectively. For Type II device with a smallest p-pillar width near the drain, they can be enhanced further and reach to 4.9 GHz and 83 V. These experimental results suggest that the SJ-LDMOS can be used in the RF power amplifiers. (C) 2016 The Japan Society of Applied Physics
Implementation of Surface Acoustic Wave Vapor Sensor Using Complementary Metal-Oxide-Semiconductor Amplifiers
(2009-04-01)
Chiu, Chia-Sung
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Chang, Ching-Chun
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Ku, Chia-Lin
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Peng, Kang-Ming
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Jeng, Erik S.
A surface acoustic wave (SAW) vapor sensor is presented in this work. A SAW delay line oscillator on quartz substrate with the high gain complementary metal-oxide-semiconductor (CMOS) amplifier using a two-poly-two-metal (2P2M) 0.35 mu m process was designed. The gain of the CMOS amplifier and its total power consumption are 20 dB and 70 mW, respectively. The achieved phase noise of this SAW oscillator is -150 dBc/Hz at 100 kHz offset. The sensing is successfully demonstrated by a thin poly(epichlorohydrin) (PECH) polymer film on a SAW oscillator with alcohol vapor. This two-in-one sensor unit includes the SAW device and the CMOS amplifier provides designers with comprehensive model for using these components for sensor circuit fabrication. Furthermore it will be promising for future chemical and biological sensing applications. (C) 2009 The Japan Society of Applied Physics
Investigation of Hot-Carrier Stress Effect on High-Frequency Performance of Laterally Diffused Metal-Oxide-Semiconductor Transistors
(2012-02-01)
Chen, Kun-Ming
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Mou, Zong-Wen
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Kuo, Hao-Chung
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Chiu, Chia-Sung
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Chen, Bo-Yuan
The hot-carrier stress effects on the high-frequency performance characteristics of laterally diffused metal-oxide-semiconductor (LDMOS) transistors were investigated. A constant bias channel hot-carrier stress was applied at room temperature. After applying 3 h of hot-carrier stress, the on-resistance and saturation drain current degradations are 18 and 9%, respectively. However, the degradations of the cutoff frequency and maximum oscillation frequency were less than 2% when the devices were biased before the onset of quasi-saturation. In addition, we found that the degradations of high-frequency parameters are not related to the change in transconductance but to the changes in gate capacitances. Finally, S-parameter variations under hot-carrier stress were also examined in this study. The observations of S-parameter variations are important for RF power amplifier design. (C) 2012 The Japan Society of Applied Physics
LDMOS Transistor High-Frequency Performance Enhancements by Strain
(2012-04-01)
Chen, Kun-Ming
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Huang, Guo-Wei
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Chen, Bo-Yuan
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Chiu, Chia-Sung
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Hsiao, Chih-Hua
The effects of mechanical stress on the dc and high-frequency performances of laterally diffused MOS (LDMOS) transistors with different layout structures were investigated by using the wafer bending method. A 3.1% peak cutoff frequency (f(T)) enhancement is achieved for the multifinger device under 0.051% biaxial tensile strain. For LDMOS with annular layout, the f(T) enhancement is increased to 3.7% due to the various channel directions. Our results suggest the strain technology can be adopted in LDMOS for RF applications. The transconductance and gate capacitance were also extracted to clearly demonstrate the f(T) variations.
Nonlinear Behavior Characterization of RF Active Devices Using Impedance-dependence X-parameters
(2010-01-01)
Chiu, Chia-Sung
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Lin, Shu-Yu
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Chen, Bo-Yuan
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Chen, Kun-Ming
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Huang, Guo-Wei
This paper presents a nonlinear characterization of active device using polyharmonic distortion model formed by X-parameters. By means of the Polyharmonic distortion model characterized via nonlinear vector network analyzer makes it possible to achieve a good agreement between measured and simulated data in terms of power gain and intermodulation. Furthermore, large-signal validation of this model via X-parameters also shows a good match with measurements in RF LDMOS transistor without optimization. Results show that the X-parameters from nonlinear vector network analyzer appear to be a better method for nonlinear characterization.
Performance improvement and scalability of nonoverlapped implantation nMOSFETs with charge-trapping spacers as nonvolatile memories
(2007-12-01)
Jeng, Erik S.
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Chiu, Chia-Sung
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Hon, Chih-Hsueh
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Kuo, Pai-Chun
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Fan, Chen-Chia
This paper explores gate-to-source/drain nonoverlapped implantation (NOI) devices that function as nonvolatile memories (NVMs) by trapping charges in the silicon nitride spacers. These NOI nMOSFET devices with improved NVM characteristics were simulated and demonstrated. For a 0.8 V shift in the threshold voltage, the programming and erasing speeds of NOI devices are as fast as 40 and 60 mu s, respectively. Improvements of other related NVM characteristics, including charge retention and cycling endurance,, are reported. Finally, the scalability of NOI devices is simulated and discussed.
Performance Improvement in RF LDMOS Transistors Using Wider Drain Contact
(2013-09-01)
Chen, Kun-Ming
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Chen, Bo-Yuan
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chen, Chun-Hao
In this letter, we proposed a new layout structure for RF laterally diffused metal-oxide-semiconductor (LDMOS) transistors. In a multifinger layout, the drain contact region was designed to be wider than the channel region. The wider drain increases the equivalent drift region width to reduce the drift resistance and suppress the quasi-saturation effect. We found that the wide-drain multifinger LDMOS devices have lower on-resistance, higher cutoff frequency, higher maximum oscillation frequency, and better power performances than the standard multifinger ones.
Power Improvement for 65nm nMOSFET with High-Tensile CESL and Fast Nonlinear Behavior Modeling
(2010)
Chiu, Chia-Sung
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Chen, Kun-Ming
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Huang, Guo-Wei
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Lin, Shu-Yu
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Chen, Bo-Yuan
In this paper, the power gain improvements by stress contact etch stop layer (CESL) in a 65-nm nMOSFET were studied. Compared to the conventional nMOSFET, the device with CESL stress shows an extra 6% power gain enhancement for the increased stress in the channel region. This study also presents the polyharmonic distortion (PHD) model extraction by X-parameters measurement when the power transistor was designed to work far from 50 ohms. By mean of this model, the accurate nonlinear behaviors of nMOSFET were obtained rapidly.
RF power FinFET transistors with a wide drain-extended fin
(2017-04-01)
Chen, Bo-Yuan
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Chen, Kun-Ming
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Chiu, Chia-Sung
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Huang, Guo-Wei
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Chen, Hsiu-Chih
Drain-extended FinFET transistors for RF power applications have been fabricated and is presented in this paper. Power FinFETs with a wide drain extension are proposed to reduce the drain resistance. Compared with conventional drain-extended FinFETs, our proposed new devices exhibit lower on-resistances and better high-frequency performances while keeping a similar breakdown voltage. The enhancements of the on-resistance and peak cutoff frequency are 16 and 56%, respectively, under an optimal drain-extension layout. These experimental results suggest that FinFET transistors with a wide drain extension could be used for RF power applications, increasing the possibility of integrating RF power parts into future FinFET system-on-a-chip technologies. (C) 2017 The Japan Society of Applied Physics