Browsing by Author "Chiu, Yu-Chien"

Now showing 1 - 20 of 30

Amorphous bilayer TiO2-InGaZnO thin film transistors with low drive voltage
(2014-09-01)
Hsu, Hsiao-Hsuan
;
Cheng, Chun-Hu
;
Chiou, Ping
;
Chiu, Yu-Chien
;
Chang, Chun-Yen
This paper describes a high-performance thin-film transistor (TFT) fabricated using TiO2 and InGaZnO semiconducting layers. Favorable transistor characteristics, including a low threshold voltage of 0.45 V, a small subthreshold swing of 174 mV/decade, and a high field effect mobility of 19 cm(2)/V s at a low drive voltage of <2 V, were achieved. This favorable performance mainly resulted from the combined effect of the high-dielectric-constant gate dielectric and the TiO2-InGaZnO active semiconductor bilayer, which reduced the operating voltage, enhanced the device mobility, and improved the transistor gate swing. This TiO2-InGaZnO TFT exhibits great potential for future high-speed and high-resolution display applications. (C) 2014 Elsevier Ltd. All rights reserved.
An Oxygen Gettering Scheme for Improving Device Mobility and Subthreshold Swing of InGaZnO-Based Thin-Film Transistor
(2014-09-01)
Hsu, Hsiao-Hsuan
;
Chang, Chun-Yen
;
Cheng, Chun-Hu
;
Chiou, Shan-Haw
;
Huang, Chiung-Hui
This study involved developing a low-power and high-mobility metal-oxide thin-film transistor that incorporated a bilayer IGZO/IGZO:Ti semiconductor material. Compared with control metal-oxide TFTs, the bilayer IGZO TFT through thickness modulation of IGZO: Ti can reach the smallest subthreshold swing (85 mV/decade) and the highest field effect mobility (49 cm(2)/Vs) at a drive voltage of <3 V. This performance level improvement can be attributed to the gettering effect caused by the IGZO: Ti capping layer and its dual advantages, which enhance device mobility and improve gate swing.
Bipolar Conduction in Tin-Oxide Semiconductor Channel Treated by Oxygen Plasma for Low-Power Thin-Film Transistor Application
(2016-03)
Chen, Po-Chun
;
Wu, Yung-Hsien
;
Zheng, Zhi-Wei
;
Chiu, Yu-Chien
;
Cheng, Chun-Hu
In this paper, we investigated the bipolar conduction mechanism in thin-film transistors (TFTs) with oxygen plasma treatment on tin-oxide channel. The optimized p-type thin-oxide TFTs showed an on/off ratio of >10(4), a threshold voltage of -1.05 V, and a field-effect mobility of 2.14 cm(2).V-1.s(-1). By increasing the exposure time of oxygen plasma, excess oxygen was incorporated to thin-oxide channel and converted thin monoxide to oxygen-rich n-type thin dioxide, which in turn led to n-type operation. It indicated that oxygen plasma was the critical factor to determine oxygen concentration, oxygen vacancies, metal ions and channel polarity. This proposed oxygen-content tuning through plasma treatment approach shows great promise in simplification of TFT process that can achieve n-type and p-type TFTs under the same device process.
Correlation of thermal annealing effect, crystallinity and electrical characteristics in c-axis crystallized InGaZnO thin-film transistors
(2015-09-15)
Hsu, Hsiao-Hsuan
;
Yen, Shiang-Shiou
;
Chiu, Yu-Chien
;
Chiou, Ping
;
Chang, Chun-Yen
A low off-state current of 1.6 x 10(-14) A/mu m and a small subthreshold gate swing of 152 mV/decade were achieved in a novel thin film transistor using a c-axis crystallized InGaZnO semiconductor that could be obtained at a low substrate temperature range of 150 degrees C. From experimental results, we found that the lowered off-state current is mainly attributed to the formation of rich Ga-O bonds to reduce oxygen vacancies, and the c-axis crystallized structure of IGZO to increase the potential barrier on the source side due to the increase of local trap states at the grain boundary. (C) 2015 Elsevier B.V. All rights reserved.
Energy-Efficient Versatile Memories With Ferroelectric Negative Capacitance by Gate-Strain Enhancement
(2017-08-01)
Chiu, Yu-Chien
;
Cheng, Chun-Hu
;
Liou, Guan-Lin
;
Chang, Chun-Yen
;
電子工程學系及電子研究所
In this brief, we reported a ferroelectric versatile memory with strained-gate engineering. The versatile memory with high-strain-gate showed a >40% improvement on ferroelectric hysteresis window, compared to low-strain case. The high compressive stress induced from high nitrogen-content TaN enhances monoclinic-to-orthorhombic phase transition to reach stronger ferrolectric polarization and lower depolarization field. The versatile memory featuring ferroelectric negative capacitance exhibited excellent transfer characteristics of the sub-60-mVdec subthreshold swing, ultralow off-state leakage of <1fA/mu m and > 108 on/off current ratio. Furthermore, the ferroelectric versatile memory can be switched by +/- 5 V under 20-ns speed for a long endurance cycling (similar to 10(12) cycles). The low-power operation can be ascribed to the amplification of the surface potential to reach the strong inversion and fast domain polarization at the correspondingly low program/erase voltages.
Experimental Observation of Negative Capacitance Switching Behavior in One-Transistor Ferroelectric Versatile Memory
(2017-10-01)
Cheng, Chun-Hu
;
Chiu, Yu-Chien
;
Liou, Guan-Lin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, we investigated the negative capacitance behavior of novel ferroelectric versatile memory with low-voltage-driven and fast ferroelectric switching. The combined storage mechanism strengthened the stability of ferroelectric polarization by interface aligned dipoles. The simulation results of first principle calculation indicated that the monoclinic-like orthorhombic phase of ferroelectric hafnium oxide facilitated the occurrence of S-shaped negative capacitance behavior. Furthermore, the control of phase transition may affect ferroelectric property and negative capacitance effect during program and erase states.
Fast Low-Temperature Plasma Process for the Application of Flexible Tin-Oxide-Channel Thin Film Transistors
(2017-09-01)
Chen, Po-Chun
;
Chiu, Yu-Chien
;
Zheng, Zhi-Wei
;
Lin, Ming-Huei
;
Cheng, Chun-Hu
In this study, we demonstrated a p-type and n-type SnO TFTs on flexible polyimide substrate. The fabricated p-type SnO TFT showed a high I-on/I-off of 5.7 x 10(5) and a high mu(FE) of 10.7 cm(2) V-1 s(-1). Through optimizing the oxygen plasma condition, the n-type channel TFT transfered from prime p-type channel exhibits excellent characteristics, including a high on/off current ratio of 6.6 x 10(3), a low threshold voltage of -0.13 V, and a very high field-effect mobility of 28 cm(2) V-1 s(-1). This proposed low-temperature oxygen plasma treatment shows the potential in simplification of TFT process that can achieve n-type and p-type TFTs under the same device process.
Gettering Effect Induced by Oxygen-Deficient Titanium Oxide in InZnO and InGaZnO Channel Systems for Low-Power Display Applications
(2016-03)
Yen, Shiang-Shiou
;
Chiu, Yu-Chien
;
Cheng, Chun-Hu
;
Chen, Po-Chun
;
Yeh, Yu-Chen
This paper reported the IGZO and IZO thin-film transistor (TFT) with titanium-oxide semiconductor as channel capping layer. After the TiOx Gettering process, the oxygen vacancies in IGZO channel were successfully modified to maximize the carrier concentration and device mobility. The superior transfer characteristics included a low sub-threshold swing of 79 mV/decade, a very high mobility of 68 cm(2)/V.s, and good on/off-current ratio of 5.61 x 10(6). However, the IZO channel with nano-crystallized grains and without Ga atom doping showed unfavorable transistor characteristics. In addition to apparently degraded transfer properties, the spontaneously oxidized TiOx capping layer also lead to an increase of channel parasitic resistance that limits the output driving current. Therefore, we believe that the existence of Ga-O bonds among IGZO channel would be helpful to stabilize oxygen diffusion behavior and electric structure during Gettering process.
High holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layer
(2016-04)
Yen, Shiang-Shiou
;
Cheng, Chun-Hu
;
Lan, Yu-Pin
;
Chiu, Yu-Chien
;
Fan, Chia-Chi
High electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 mu m 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology. (C) 2016 The Japan Society of Applied Physics
High holding voltage segmentation stacking silicon-controlled-rectifier structure with field implant as body ties blocking layer
(2016-04-01)
Yen, Shiang-Shiou
;
Cheng, Chun-Hu
;
Lan, Yu-Pin
;
Chiu, Yu-Chien
;
Fan, Chia-Chi
High electrostatic discharge (ESD) protection robustness and good transient-induced latchup immunity are two important issues for high voltage integrate circuit application. In this study, we report a high-voltage-n-type-field (HVNF) implantation to act as the body ties blocking layer in segmented topology silicon-controlled-rectifier (SCR) structure in 0.11 mu m 32 V high voltage process. This body ties blocking layer eliminate the elevated triggered voltage in segmented technique. Using a large resistance as shunt resistor in resistor assisted triggered SCRs stacking structure, the double snapback phenomenon is eliminate. The series SCR could be decoupled a sufficient voltage drop to turned-on when a very low current flow through the shunt resistor. The holding voltage and the failure current of 22 V and 3.4 A are achieved in the best condition of segmented topology SCR stacking structure, respectively. It improves the latchup immunity at high voltage ICs application. On the other hand, the triggered voltage almost keep the same value which is identical to SCR single cell without using segmented topology. (C) 2016 The Japan Society of Applied Physics
High Mobility Field-Effect Thin Film Transistor Using Room-Temperature High-kappa Gate Dielectrics
(2014-10-01)
Hsu, Hsiao-Hsuan
;
Chang, Chun-Yen
;
Cheng, Chun-Hu
;
Chen, Po-Chun
;
Chiu, Yu-Chien
This paper reports an InGaZnO thin-film transistor (TFT) that involves using fully room-temperature gate dielectrics on a flexible substrate. The wide bandgap dielectrics of HfO2 and Y2O3 exhibited favorable adhesion properties on a flexible substrate compared with conventional low-kappa SiO2 film. Based on the experimental results, the room-temperature IGZO/HfO TFTs demonstrated effective device integrity, and achieve a low drive voltage of < 2 V, a low threshold voltage of 0.46 +/- 006 V, a low sub-threshold swing of 110 +/- 6 mV/decade and an extremely high mobility of 60.2 +/- 32 cm(2)/V s. The excellent performance of this TFT indicated that it demonstrates considerable potential for active-matrix liquid crystal display applications requiring low power consumption and a high driving current.
High Speed Negative Capacitance Ferroelectric Memory
(2017-01-01)
Chang, Chun-Yen
;
Fan, Chia-Chi
;
Liu, Chien
;
Chiu, Yu-Chien
;
Cheng, Chun-Hu
This work experimentally demonstrated a one-transistor ferroelectric versatile memory with the multi-technique integration of negative-capacitance mechanism, ferroelectric polarization effect and metal-strained engineering. The negative-capacitance versatile memory featured a steep sub-60mV/dec subthreshold swing, fast 20-ns switching speed and long 1012 cycled endurance. We successfully demonstrated that the metal-gate-induced strain could help to improve ferroelectric phase transformation. The excellent endurance characteristics could be ascribed to efficient ferroelectric negative-capacitance switching under low program/erase voltages.
Impact of Ferroelectric Domain Switching in Nonvolatile Charge-Trapping Memory
(2017-01-01)
Fan, Chia-Chi
;
Chiu, Yu-Chien
;
Liu, Chien
;
Liou, Guan-Lin
;
Lai, Wen-Wei
In this work, we proposal a ferroelectric domain to enhance program/erase/read efficiency of conventional charge-trapping nonvolatile memory. The ferroelectric-domain-dominated HfZrO/HfON memory shows the better subthreshold characteristics than control charge-trapping structure (HfO2/HfON). Additionally, the memory speed with ferroelectric polarization (similar to 800ns) is more than three orders of magnitude faster than that of control trapping type.
Impact of Nanoscale Polarization Relaxation on Endurance Reliability of One-Transistor Hybrid Memory Using Combined Storage Mechanisms
(2015)
Chiu, Yu-Chien
;
Chang, Chun-Yen
;
Hsu, Hsiao-Hsuan
;
Cheng, Chun-Hu
;
Lee, Min-Hung
We demonstrate a novel hybrid nonvolatile memory integrated with a charge trapping mechanism and a ferroelectric polarization effect. The hybrid memory features a large threshold voltage window of 2V, fast 20-ns program/erase time, tight switching margin, and long 10(12)-cycling endurance at 85 degrees C. Such excellent endurance reliability at 85 degrees C can be ascribed to the introduction of charge-trapping node into the design of memory structure that not only weakens temperature-dependent polarization relaxation, but also improves high-temperature endurance reliability.
Improved Electrical Characteristics and Reliability of Multi-Stacking PNPN Junctionless Transistors Using Channel Depletion Effect
(2017-01-01)
Lin, Ming-Huei
;
Shih, Yi-Jia
;
Liu, Chien
;
Chiu, Yu-Chien
;
Fan, Chia-Chi
This work demonstrates a novel multi-stacking PNPN channel structure for nanowire junctionless transistor. With the multi-PNPN channel structure, the design of multi-stacking PNPN junctions can promote the p-type channel layer to achieve fully depleted channel, accompanied with the excellent electrical performances on a steep subthreshold swing of 77 mV/dec and a high on/off current ratio of >10(7). Besides, utilizing with the constant-voltage-stress measurement, the multi-PNPN channel junctionless FETs with a robust stress reliability was demonstrated.
Improved Thermal Stability and Stress Immunity in Highly Scalable Junctionless FETs Using Enhanced-Depletion Channels
(2018-12-05)
Liu, Chien
;
Cheng, Chun-Hu
;
Lin, Ming-Huei
;
Shih, Yi-Jia
;
Hung, Yu-Wen
In this work, we report a novel multi-PNPN-channel junctionless transistor with short channel length of 60nm. The multi-PNPN junctionless transistor exhibits the larger drive current of > 1 mu A/mu m, the steeper turn-on switching of 77 mV/decade, and the higher on/off current ratio of > 10(7) than the hybrid PN channel device under the same gate overdrive. The improved performance is mainly attributed to the enhanced depletion effect of multi-PNPN channel to optimize the electric field modification of surface p-channel. The stronger immunity to constant-voltage stress is also obtained for multi-PNPN channel due to the lower lateral electric field near drain side to reduce the impact ionization ratio. (C) 2018 The Electrochemical Society.
Improvement of dielectric flexibility and electrical properties of mechanically flexible thin film devices using titanium oxide materials fabricated at a very low temperature of 100 degrees C
(2015-09-15)
Hsu, Hsiao-Hsuan
;
Chiu, Yu-Chien
;
Chiou, Ping
;
Cheng, Chun-Hu
;
電子工程學系及電子研究所
In this works, we investigated a Ti-O material system integrating with InGaZnO thin film transistor. The Ti-O material system with high bond enthalpy can be functionalized by tuning the amount oxygen vacancies to reach the applicable requirements of gate dielectric and channel. Compared to control IGZO TFTs, the flexible TiOx/IGZO TFT reaches a smaller sub-threshold swing (SS) of 125 mV/decade and a higher field effect mobility of 61 cm(2)/V s at a very low operating voltage of 1.5 V. Besides, only slight performance degradation was found after bending test. (C) 2014 Elsevier B.V. All rights reserved.
Influence of plasma fluorination on p-type channel tin-oxide thin film transistors
(2017-06-15)
Chen, Po-Chun
;
Chiu, Yu-Chien
;
Zheng, Zhi-Wei
;
Cheng, Chun-Hu
;
Wu, Yung-Hsien
This paper describes a high-performance p-type tin-oxide (SnO) thin film transistor (TFT) using fluorine plasma treatment on the SnO active channel layer. The influence of fluorine plasma treatment for this p-type SnO TFT device was also investigated. Through tuning the fluorine plasma power treated on the SnO active channel layer at low temperature, the optimal p-type SnO TFT device exhibits a very high on/off current ratio of 9.6 x 10(6), a field-effect mobility of 2.13 cm(2) V-1 s(-1), a very low subthreshold swing of 106 mV/dec and an extremely low off-state current of 1 pA at a low driven voltage of <3 V. These good characteristics can be attributed to fluorine plasma treatment on p-type SnO channel that reduced crystallized channel roughness and passivated oxygen vacancies and interface traps. This high-performance p-type SnO TFT device using fluorine plasma treatment on the active channel shows great promise for future high-resolution and high-speed display applications. (C) 2016 Elsevier B.V. All rights reserved.
Interface Polarization Fluctuation Effect of Ferroelectric Hafnium-Zirconium-Oxide Ferroelectric Memory with Nearly Ideal Subthreshold Slope
(2015)
Chiu, Yu-Chien
;
Cheng, Chun-Hu
;
Fan, Chia-Chi
;
Chen, Po-Chun
;
Chang, Chun-Yen
Investigation of Double-Snapback Characteristic in Resistor-Triggered SCRs Stacking Structure
(2017-10-01)
Yen, Shiang-Shiou
;
Cheng, Chun-Hu
;
Fan, Chia-Chi
;
Chiu, Yu-Chien
;
Hsu, Hsiao-Hsuan
Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current-voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a 0.11 mu m32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure.