Browsing by Author "Chou, K. I."

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Achieving low sub-0.6-nm EOT in gate-first n-MOSFET with TiLaO/CeO2 gate stack
(2013-04-01)
Cheng, C. H.
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Chou, K. I.
;
Chin, Albert
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
We report a gate-first TiLaO/CeO2 n-MOSFET with an equivalent oxide thickness (EOT) of only 0.56 nm and threshold voltage (V-t) of 0.31 V. This small EOT MOSFET was achieved by employing high-kappa CeO2 interfacial layer with high bond enthalpy (795 kJ/mol) to replace low-kappa SiO2 with close bond enthalpy (800 kJ/mol). The cerium silicate can aggressively scale EOT down to sub-0.6-nm EOT region without increasing gate leakage, which is urgently needed for 16 nm technology node. (C) 2013 Elsevier Ltd. All rights reserved.
Gate-first n-MOSFET with a sub-0.6-nm EOT gate stack
(2013-09-01)
Cheng, C. H.
;
Chou, K. I.
;
Chin, A.
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We report a self-aligned and gate-first TiLaO/La2O3 n-MOSFET with an equivalent oxide thickness (EOT) of 0.57 nm and low threshold voltage (V-t) of 0.3 V. The small EOT MOSFET can be reached using La-based interfacial layer with strong bond enthalpy (La-O, 799 kJ/mol) to suppress the formation of defect-rich low- interfacial layer and simultaneously block titanium atom inter-diffusion to avoid additional EOT increase. This gate-first low-EOT MOSFET exhibits the potential to integrate with current CMOS process. (C) 2013 Elsevier B.V. All rights reserved.
Low power resistive random access memory using interface-engineered dielectric stack of SiOx/a-Si/TiOy with 1D1R-like structure
(2014-01-01)
Cheng, Chun-Hu
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Chou, K. I.
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Zheng, Zhi-Wei
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Hsu, Hsiao-Hsuan
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電子工程學系及電子研究所
In this study, we report a resistive random access memory (RRAM) using trilayer SiOx/a-Si/TiOy film structure. The low switching energy of <10 pJ, highly uniform current distribution (<13% variation), fast 50-ns speed and stable cycling endurance for 10(6) cycles are simultaneously achieved in this RRAM device. Such good performance can be ascribed to the use of interface-engineered dielectric stack with 1D1R-like structure. The SiOx tunnel barrier in contact with top Ni electrode to form diode-like rectifying element not only lowers self-compliance switching currents, but also improves cycling endurance, which is favorable for the application of high-density 3D memory. (C) 2013 Elsevier B. V. All rights reserved.
Low-Voltage InGaZnO Thin Film Transistors with Small Sub-Threshold Swing
(2015-02-01)
Cheng, C. H.
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Chou, K. I.
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Hsu, H. H.
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We demonstrate a low-voltage driven, indium gallium zinc oxide thin-film transistor using high-kappa LaAlO3 gate dielectric. A low V-T of 0.42 V, very small sub-threshold swing of 68 mV/dec, field-effect mobility of 4.1 cm(2)Ns and low operation voltage of 1.4 V were reached simultaneously in LaAlO3/IGZO TFT device. This low-power and small SS TFT has the potential for fast switching speed and low power applications.
Ni/GeOx/TiOy/TaN RRAM on Flexible Substrate With Excellent Resistance Distribution
(2013-04-01)
Chou, K. I.
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Cheng, C. H.
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Zheng, Z. W.
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Liu, Ming
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Chin, Albert
Excellent device-to-device distribution was achieved in high-performance Ni/GeOx/TiOy/TaN resistive random access memory on low-cost flexible plastics, with low 30-mu W switching power (9 mu A at 3 V; -1 mu A at -3 V), 10(5) cycling endurance, and good retention at 85 degrees C. These were ascribed to bulk transport property by tunneling between traps, forming-free resistive switching, and the less destructive low power switching.