Browsing by Author "Chou, Mao-Hsuan"

Now showing 1 - 2 of 2

A 0.1-3GHz Cell-Based Fractional-N All Digital Phase-Locked Loop Using Delta Sigma Noise-Shaped Phase Detector
(2013-01-01)
Liu, Yao-Chia
;
Chen, Wei-Zen
;
Chou, Mao-Hsuan
;
Tsai, Tsung-Hsien
;
Lee, Yen-Wei
A 0.1-3 GHz, cell-based, fractional-N ADPLL with Delta Sigma noise-shaped phase detector is presented. By dithering the reference phase and quantization phase error through an additional feedback path, linear phase detection and zero stabilization are accomplished without resort to sophisticated time to digital converter (TDC). The measured rms jitter from a 3GHz carrier is 1.9 ps with a multiplication factor of 60. Implemented in TSMC 40nm general purpose superb CMOS technology, the chip size is 280um x 240um.
A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application
(2014-04-01)
Lin, Mu-Shan
;
Tsai, Chien-Chun
;
Chang, Chih-Hsien
;
Huang, Wen-Hung
;
Hsu, Ying-Yu
A 1 Tbit/ s bandwidth PHY is demonstrated through CoWoS(TM) platform. Two chips: SOC and embedded DRAM ( eDRAM), have been fabricated in TSMC 40 nm CMOS technology and stacked on a silicon interposer chip. 1024 DQ buses operating at 1.1 Gbit/ s with VDDQ = 0.3 V are proven between SOC chip and eDRAM chip in experimental results with 1 mm signal trace length on the silicon interposer. A novel timing compensation mechanism is presented to achieve a low- power and small area eDRAM PHY that excludes PLL/ DLL but retains good timing margin. Another data sampling alignment training approach is employed to enhance timing robustness. A compact low- swing IO also achieves power efficiency of 0.105 mW/ Gbps.