Browsing by Author "Guo, JC"

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0.13 mu m low voltage logic based RF CMOS technology with 115GHz f(T) and 80GHz f(MAX)
(2003)
Guo, JC
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Huang, CH
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Chan, KT
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Lien, WY
;
Wu, CM
Superior RF CMOS of 115GHz f(T) and 80GHz f(max) has been realized by 0.13mum low voltage logic based RF CMOS technology by aggressive device scaling and optimized layout. NFmin of 2.2dB at 10GHz is achieved even without deep N-well and ground-shielded signal pad. P,dB of near 10dBm can fit bluetooth requirement and 55% PAE at 2.4 GHz address the good potential of sub-100nm CMOS for low voltage RF power applications.
0.13-mu m low-kappa-Cu CMOS logic-based technology for 2.1-Gb high data rate read-channel
(2004-05-01)
Guo, JC
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Lien, WY
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Tsai, TL
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Chen, SM
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Wu, CM
High-performance analog/digital elements have been successfully fabricated bya 0.13-mum low-kappa-Cu logic-based mixed-signal CMOS process in a single chip to enable a 2.1-Gb/s read-channel for hard disk drives that is a record-high data rate supported by fully CMOS solution. The high-performance analog devices demonstrate superior drivability, matching, noise immunity, and reliability by a unique dual-gate oxide module to support the aggressive oxide thickness scaling and maintain promisingly good reliability in all aspects.
0.13-mu m RF CMOS and varactors performance optimization by multiple gate layouts
(2004-12-01)
Ho, CC
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Kuo, CW
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Chan, Y
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Lien, WY
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Guo, JC
0.13-mum radio frequency (RF) CMOS devices with multifinger gate structure have been fabricated by the standard logic process, and the measured effective gate-length is 80 nm. Extensive RF characterization has been done to obtain cutoff frequency (f(T)), associated power gain cutoff frequency (f), minimum noise figure (NFmin), output power (P-out), and power added efficiency (PAE) for RF circuit design and to explore the optimized gate layout in terms of the extracted RF device parameters. Our important finding to be reported in this paper is that an optimized unit finger width (W-F) exists by trade-off among f(T), f(.max), NFmin, P-out, and PAE. Under fixed total width to achieve the same current drivability (I-ds), the smaller W-F and the larger finger number (N-F) leads to higher f(max) but lower f(T) due to trade-off between gate resistance (R-g) and parasitic gate capacitance. As for NFmin complicated by f(T) and R-g, counter-balance between parasitic gate capacitance and R-g leads to nearly constant NFmin. w.r.t. various splits of (W-F, N-F). Regarding P-out and PAE, W-F of 4 mum and NF of 18 is the optimized layout parameter, which offers the maximum P-out of around 11 dBm and PAE of 30.5% at 5.8 GHz. The performances of accumulation-mode MOS varactors with different gate layout structures are also investigated in this report. Since the same area varactors with different gate layout may result in different parasitic resistance and fringing capacitance, which will affect the capacitance tuning range and the associated Q-factor. The maximum Q-factor is about 59 of the 120 mum(2) gate area varactor, and its tuning range is from 210 IF to 1.64 pF, where the maximum C-max/C-min ratio is about 7.8.
A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects
(2006-03-01)
Guo, JC
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Tan, TY
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
A new T-model has been developed to accurately simulate the broadband characteristics of on-Si-chip spiral inductors, up to 20 GHz. The spiral coil and substrate RLC networks built in the model play a key role responsible for conductor loss and substrate loss in the wideband regime, which cannot be accurately described by the conventional pi-model. Good match with the measured S-parameters, L (omega), Re (Z(in), (omega)), and Q (omega) proves the proposed T-model. Besides the broadband feature, scalability has been justified by good match with a linear function of coil numbers for all model parameters employed in the RLC networks. The satisfactory scalability manifest themselves physical parameters rather than curve fitting. A parameter extraction flow is established through equivalent circuit analysis to enable automatic parameter extraction and optimization. This scalable inductor model will facilitate optimization design of on-chip inductor and the accuracy proven up to 20 GHz can improve RF circuit simulation accuracy demanded by broadband design.
A broadband and scalable model for on-chip inductors incorporating substrate and conductor loss effects
(2005)
Guo, JC
;
Tan, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new T-model is developed to accurately simulate the broadband characteristics of on-Si-chip spiral inductors, up to 20GHz. The spiral coil and substrate RLC networks built in the model play a key role responsible for conductor loss and substrate loss in the wideband regime, which cannot be accurately described by the conventional pi-model. Good match with the measured S-parameters, L(omega), Re(Z(in)(omega)), and Q(omega) proves the proposed T-model. Besides the broadband feature, scalability is justified by the good match with a linear function of coil numbers for all model parameters employed in the RLC networks. The satisfactory scalability manifest themselves physical parameters rather than curve fitting. A parameter extraction flow is established through equivalent circuit analysis to enable automatic parameter extraction and optimization. This scalable inductor model will facilitate optimization design of on-chip inductor and the accuracy proven up to 20GHz can improve RF circuit simulation accuracy demanded by broadband design.
A lossy substrate model for sub-100nm, super-100 GHz f(T) RF CMOS noise extraction and modeling
(2005)
Guo, JC
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Lin, YM
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A lossy substrate model is developed to accurately simulate the measured RF noise of 80 nm, super-100 GHz f(T) nMOSFETs. Substrate RLC network built in the model plays a key role responsible for the nonlinear frequency response of noise in 1 similar to 18 GHz regime, which didn't follow the typical thermal noise theory. Good match with the measured S-parameters, Y-parameters, and N-min before de-embedding proves the lossy substrate modell. The intrinsic RF noise can be extracted easily and precisely by the lossy substrate de-embedding using circuit simulation. The accuracy has been justified by good agreement in terms of I-d, g(m), Y-parameters, and fT under wide range of bias conditions and operating frequencies. The extracted intrinsic NFmin as low as 0.6 similar to 0.7dB at 10GHz indicates the advantages of super-100 GHz f(T) offered by the sub-100nm multi-finger nMOS. The frequency dependence of noise resistance R-n suggests the substrate RC coupling induced excess channel thermal noise apparent in 1 similar to 10 GHz regime. The study provides useful guideline for low noise and low power design by using sub-100nm RF CMOS technology.
A new lossy substrate de-embedding method for sub-100 nm RF CMOS noise extraction and modeling
(2006-02-01)
Guo, JC
;
Lin, YM
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new equivalent circuit method is proposed in this paper to de-embed the lossy substrate and lossy pads' parasitics; from the measured RF noise of multifinger MOSFETs with aggressive gate length scaling down to 80 run. A new RLC network model is subsequently developed to simulate the lossy substrate and lossy pad effect. Good agreement has been realized between the measurement and simulation in terms of S-parameters and four noise parameters, NFmin,, (minimum noise figure), R, (noise resistance), Re(Y-sopt), and Im(Y-sopt) for the sub-100-nm RF nMOS devices. The intrinsic NFmin extracted by the new de-embedding method reveal that NFmin at 10 GHz can be suppressed to below 0.8 dB for the 80-nm nMOS attributed to the advancement of f(T) to 100-GHz level and the effectively reduced gate resistance by multifinger structure.
A simple transmission line de-embedding method for accurate RF CMOS noise modeling
(2004)
Guo, JC
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Huang, CH
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Lien, WY
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Wu, CM
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電子工程學系及電子研究所
We propose a simple method to de-embed the transmission line and pads' parasitics from the measured RF noise of multi-finger MOSFETs with aggressive gate length scaling down to 80 nm and 65 nm respectively. Good agreement has been realized between measurement and simulation in terms of S-parameters and NFmin (minimum noise figure) for RF CMOS devices with various finger numbers by using this novel de-embedding method. The extracted NFmin after de-embedding matches well with the published noise correlation matrix method but is relatively simple without resort to complicated matrices calculation.
Direct observation of the lateral nonuniform channel doping profile in submicron MOSFET's from an anomalous charge pumping measurement results
(1995)
Chung, SS
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Cheng, SM
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Lee, GH
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Guo, JC
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電子工程學系及電子研究所
Low-power and high-linearity mixer design using complex transconductance equivalent circuit
(2005)
Zhan, WC
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Kuo, CN
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Guo, JC
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A compact equivalent circuit using a complex transconductance is proposed for linearity design in the multiple gated transistors configuration. This complex transconductance gives better design parameters as compared to previous published analysis. Measured data show that the designed mixer has conversion gain of 4.7 dB, input return loss of 9 dB, and third-order input intercept point (IIP3) of 10.3 dBm with only 1.8 mW power dissipation under 1-V supply voltage.
Mechanisms and characteristics of oxide charge detrapping in n-MOSFET's
(1996)
Wang, TH
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Chang, TE
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Chiang, LP
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Huang, CM
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Guo, JC
Pocket implantation effect on drain current flicker noise in analog nMOSFET devices
(2004-08-01)
Wu, JW
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Cheng, CC
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Chiu, KL
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Guo, JC
;
Lien, WY
The pocket implantation effect on drain current flicker noise in 0.13 mum CMOS process based high performance analog nMOSFETs is investigated. Our result shows that pocket implantation will significantly degrade device low-frequency noise primarily because of nonuniform threshold voltage distribution along the channel. An analytical flicker noise model to account for a pocket doping effect is proposed. In our model, the local threshold voltage and the width of the pocket implant region are extracted from the measured reverse short-channel effect, and the oxide trap density is extracted from a long-channel device. Good agreement between our model and the measurement result is obtained without other fitting parameters.