Browsing by Author "HUANG, CM"

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CHARACTERIZATION AND SIMULATION OF HOT CARRIER EFFECT ON ERASING GATE CURRENT IN FLASH EEPROMS
(1995-01-01)
HUANG, CM
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WANG, TH
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CHEN, T
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PENG, NC
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CHANG, A
DEVICE AND CIRCUIT SIMULATION OF ANOMALOUS DX TRAP EFFECTS IN DCFL AND SCFL HEMT INVERTERS
(1993-11-01)
WANG, TH
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WU, SJ
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HUANG, CM
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交大名義發表
;
電子工程學系及電子研究所
An integrated device and circuit analysis has been developed to evaluate the DX trap induced anomalous transient phenomena in DCFL and SCFL AlGaAs/GaAs HEMT inverters. The slow transient effect and the hysteretic characteristics of the input-output voltage transfer function in the inverters are simulated. The result shows that in comparison with the DCFL inverter, the DX trap effects are much improved in the SCFL inverter due to its particular operational principle.
EFFECTS OF HOT-CARRIER-INDUCED INTERFACE STATE GENERATION IN SUBMICRON LDD MOSFETS
(1994-09-01)
WANG, TH
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HUANG, CM
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CHOU, PC
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CHUNG, SSS
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CHANG, TE
A two-dimensional numerical simulation including a new interface state generation model has been developed to study the performance variation of a LDD MOSFET after a dc voltage stress. The spatial distribution of hot carrier induced interface states is calculated with a breaking silicon-hydrogen bond model. Mobility degradation and reduction of conduction charge due to interface traps are considered. A 0.6 mum LDD MOSFET was fabricated. The drain current degradation and the substrate current variation after a stress were characterized to compare the simulation. A reduction of the substrate current at V(g) congruent-to 0.5 V(d) in a stressed device was observed from both the measurement and the simulation. Our study reveals that the reduction is attributed to a distance between a maximum channel electric field and generated interface states.
INTERFACE TRAP INDUCED THERMIONIC AND FIELD EMISSION CURRENT IN OFF-STATE MOSFETS
(1994)
WANG, TH
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CHANG, TE
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HUANG, CM
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
INTERFACE-TRAP EFFECT ON GATE INDUCED DRAIN LEAKAGE CURRENT IN SUBMICRON N-MOSFETS
(1994-12-01)
WANG, TH
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HUANG, CM
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CHANG, TE
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CHOU, JW
;
CHANG, CY
An interface trap assisted tunneling mechanism which includes hole tunneling from interface traps to the valence band and electron tunneling from interface traps to the conduction band is presented to model the drain leakage current in a 0.5 mu m LATID N-MOSFET. In experiment, the interface traps were generated by hot carrier stress, The increased drain leakage current due to the band-trap-band tunneling can be adequately described by an analytical expression of Delta I-d = A exp(-Bit/F) with a value of B-it of 13 MV/cm, which is much lower than that (36 MV/cm) of direct band-to-band tunneling.
MECHANISMS OF INTERFACE TRAP-INDUCED DRAIN LEAKAGE CURRENT IN OFF-STATE N-MOSFETS
(1995-04-01)
CHANG, TE
;
HUANG, CM
;
WANG, TH
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An interface trap-assisted tunneling and thermionic emission model has been developed to study an increased drain leakage current in off-state n-MOSFET's after hot carrier stress. In the model a complete band-trap-band leakage path is formed at the Si/SiO2 interface by hole emission from interface traps to a valence band and electron emission from interface traps to a conduction band. Both hole and electron emissions are carried out via quantum tunneling or thermal excitation. In this experiment, a 0.5 mu m n-MOSFET was subjected to a de voltage stress to generate interface traps. The drain leakage current was characterized to compare with the model. Our study reveals that the interface trap-assisted two-step tunneling, hole tunneling followed by electron tunneling, holds responsible for the leakage current at a large drain-to-gate bias (V-dg) The lateral field plays a major role in the two-step tunneling process. The additional drain leakage current due to band-trap-band tunneling is adequately described by an analytical expression Delta I-d = A exp (B-it/F). The value of Bit about 13 mV/cm was obtained in a stressed MOSFET, which is significantly lower than in the GIDL current attributed to direct band-to-band tunneling. As V-dg decreases, a thermionic-field emission mechanism, hole thermionic emission and electron tunneling, becomes a primary leakage path. At a sufficiently low V-dg, our model reduces to the Shockley-Read-Hall theory and thermal generation of electron-hole pairs through traps is dominant.
MODELING HOT-ELECTRON GATE CURRENT IN SI MOSFETS USING A COUPLED DRIFT-DIFFUSION AND MONTE-CARLO METHOD
(1992-11-01)
HUANG, CM
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WANG, TH
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CHEN, CN
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CHANG, MC
;
FU, J
A coupled two-dimensional drift-diffusion and Monte Carlo analysis is developed to study the hot-electron-caused gate leakage current in Si n-MOSFET's. The electron energy distribution in a device is evaluated directly from a Monte Carlo model at low and intermediate electron energies. In the portion of high electron energy where the distribution function cannot be resolved by the Monte Carlo method due to limited computational resources, an extrapolation technique is adopted with an assumption of a Boltzmann tail distribution. This assumption is based on the simulation result that although the distribution function at a high electric field shows a markedly non-Maxwellian feature globally, it has approximately an exponential decay in an energy region much above average electron energy. A particular averaging method is employed to extract the effective electron temperature in the extrapolation. Our result shows that the electron temperature obtained in this approach is about three times lower than that derived from average electron energy by means of [E] = 3/2 kT(e) in the high-field domain of a device. Channel hot electron injection into a gate via quantum tunneling and thermionic emission is simulated. Electron scattering in gate oxide is also taken into account. The calculated values of gate current are in good agreement with experimental results. In the simulation, the most serious hot electron injection occurs about 200-300 angstrom behind the peak of average electron energy due to a delayed heating effect.
STRUCTURAL EFFECT ON BAND-TRAP-BAND TUNNELING INDUCED DRAIN LEAKAGE IN N-MOSFETS
(1995-12-01)
WANG, TH
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CHANG, TE
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HUANG, CM
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YANG, JY
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CHANG, KM
The structural dependence of the hot carrier stress incurred drain leakage current via band-trap-band tunneling in off-state has been modeled and characterized in conventional S/D, DDD, and LDD n-MOSFET structures, The results shows that lateral field enhanced band-trap-band tunneling is primarily responsible for an increased drain leakage current after hot carrier stress in LDD structures while vertical field induced tunneling is dominant in conventional S/D and DDD structures.
TERRAIN EXPLORATION OF A SENSOR-BASED ROBOT MOVING AMONG UNKNOWN OBSTACLES OF POLYGONAL SHAPE
(1994-01-01)
CHEN, Z
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HUANG, CM
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交大名義發表
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資訊科學與工程研究所
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National Chiao Tung University
The problem of incremental terrain acquisition is addressed in this paper. Through a systematic planning of movements in an unknown terrain filled with polygonal obstacles, a sensor-based robot is shown to be able to incrementally build the entire terrain model; the model will be described in terms of visibility graph and visibility window. The terrain model is built area by area without any overlapping between explored areas. As a consequence, the terrain is obtained as a tessellation of disjoint star polygons. And the adjacency relations between star polygons are represented by a star polygon adjacency graph (SPAG graph). The incremental exploration process consists of two basic tasks: local exploration and exploration merging. Useful lemmas are derived for these two tasks and, then, the algorithms for the tasks are given. Examples are used to illustrate the algorithms. Two strategies for planning robot movements in the unknown terrain environment are suggested and compared. They are the depth-first search and the breadth-first search applied to the SPAG graph. Finally, the performance evaluation of the method and comparison with some existing methods are presented.
TRANSIENT SIMULATION OF EPROM WRITING CHARACTERISTICS, WITH A NOVEL HOT-ELECTRON INJECTION MODEL
(1995-02-01)
HUANG, CM
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WANG, TH
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交大名義發表
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電子工程學系及電子研究所
;
National Chiao Tung University
A two-dimensional transient simulation of EPROM writing characteristics is presented. A Monte Carlo-based hot electron injection model which accounts for Fowler-Nordheim tunneling and thermionic emission has been included in the simulation. The simulated EPROM writing transient characteristics is compared favorably with experimental results for channel lengths down to 0.5 mu m. The importance of the two injection mechanisms, thermionic emission and quantum tunneling, is evaluated.