Browsing by Author "Ho, Yingchieh"

Now showing 1 - 18 of 18

A 0.09 mu W Low Power Front-End Biopotential Amplifier for Biosignal Recording
(2012-10-01)
Tseng, Yuhwai
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Ho, Yingchieh
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Kao, Shuoting
;
Su, Chauchin
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電子工程學系及電子研究所
This work presents a biopotential front-end amplifier in which the MOS transistors are biased in subthreshold region with a supply voltage and current of 0.4-0.8 V and 0.23-1.86 mu A, respectively, to reduce the system power. Flicker noise is then removed using a chopping technique, and differential interference produced by electrode impedance imbalance is suppressed using a Gm-C filter. Additionally, the circuit is fabricated using TSMC 0.18 mu m CMOS technology with a core area of 0.77 X 0.36 mm(2). With a minimum supply voltage of 0.4 V, the measured SNR and power consumption of the proposed IC chip are 54.1 dB and 0.09 mu W, respectively.
A 0.1-0.3 V 40-123 fJ/bit/ch On-Chip Data Link With ISI-Suppressed Bootstrapped Repeaters
(2012-05-01)
Ho, Yingchieh
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Su, Chauchin
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電機工程學系
;
電控工程研究所
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Department of Electrical and Computer Engineering
This paper presents a 40-130 fJ/bit/ch on-chip data link design under a 0.1-0.3V power supply. A bootstrapped CMOS repeater is proposed to drive a 10 mm on-chip bus. It features a -V-DD to 2V(DD) swing to enhance the driving capability and reduces the sub-threshold leakage current. Additionally, a precharge enhancement scheme increases the speed of the data transmission, and a leakage current reduction technique suppresses ISI jitter. A test chip is fabricated in a 55 nm SPRVT Low-K CMOS process. The measured results demonstrate that for a 10 mm on-chip bus, the achievable data rate is 0.8-100 Mbps, and the energy consumption is 40-123 fJ per bit under 0.1-0.3 V-DD.
A 0.5V/22 mu W Low Power Transceiver IC for Use in FSC Intra-body Communication System
(2016)
Tseng, Yuhwai
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Lin, Tinyou
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Yau, Songwen
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Ho, Yingchieh
;
Su, Chauchin
This paper presents an integrated transciver chip for use in electro-static coupling intra body communication. A simplified circuit model was developed to analyze the channel characteristics. A Manchester code was used to increase signal energy. In front of the receiver, an inverter-based amplifier applies to amplify the received data. Then, a Clock and Data Recovery data develops to recover the transmitted data. The chip is fabricated using UMC 0.18um CMOS process with a chip area of 0.75 X 0.7 mm(2), power consumption of 22uW and a data transmission rate of 10M bit per second.
A 48.6-to-105.2 mu W Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications
(2014-04-01)
Hsu, Shu-Yu
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Ho, Yingchieh
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Chang, Po-Yao
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Su, Chauchin
;
Lee, Chen-Yi
A machine- learning ( ML) assisted cardiac sensor SoC ( CS- SoC) is designed for mobile healthcare applications. The heterogeneous architecture realizes the cardiac signal acquisition, filtering with versatile feature extractions and classifications, and enables the higher order analysis over traditional DSPs. Besides, the asynchronous architecture with dynamic standby controller further suppresses the system active duty and the leakage power dissipation. The proposed chip is fabricated in a 90- nm standard CMOS technology and operates at 0.5 V- 1.0 V ( 0.7 V- 1.0 V for SRAM and I/ O interface). Examined with healthcare monitoring applications, the CS- SoC dissipates 48.6/ 105.2 mu W for real- time syndrome detections of ECG- based arrhythmia/ VCG- based myocardial infarction with 95.8/ 99% detection accuracy, respectively.
A Field-Programmable Lab-on-a-Chip with Built-in Self-Test Circuit and Low-Power Sensor-Fusion Solution in 0.35 mu m Standard CMOS Process
(2015)
Lai, Kelvin Yi-Tse
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Shiu, Ming-Feng
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Lu, Yi-Wen
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Ho, Yingchieh
;
Kao, Yu-Chi
This paper presents a field programmable lab-on-a-chip (FPLOC) with microfluidics actuation, droplet location/category readback, built-in-self-test (BIST), and bioassays detection. This FPLOC is composed of 1,800 MEDA microelectrodes and integrates a set of microfluidic operations to perform droplet moving/cutting/mixing. Besides, capacitive sensing circuits are considered for system automation, droplets classification, malfunctioning microelectrodes and surface flatness testing, and biomedical detection. Implemented in 0.35 mu m standard CMOS process in 7.4mm(2), the FPLOC demonstrates microfluidic operations under 25V at 1KHz, 1.3fF resolution for droplet location/category/chip BIST maps readback at 1MHz, and 0.34fF sensitivity of capacitive measurement window for biomedical detection at 1KHz.
A Layout-Aware Test Methodology for Silicon Interposer in 3D System-in-a-Package
(2013)
Gu, Ruei-Ting
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Ho, Cheng-You
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Li, Katherine Shu-Min
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Ho, Yingchieh
;
Chen, Liang-Bi
In this paper, we propose an efficient silicon interposer pre-test methodology, which is based on the layout-aware ripple baseline algorithm for System-in-a-Package (SiP). The proposed methodology uses FPGA as our test vehicle that can test all interconnects at once without any test probes. The test interposer is synthesized according to the given layout of the target interposers, which provide microbumps and solder balls with pitches, and the test interposers are connected to the upper test side of the target interposers. Thus the test loops, which cover all interconnections of the target interposers, are built by connecting the test interposers and the target interposers. The bottom side of the target interposer is connected to an FPGA as the tester that provides test patterns to the target interposer and compares the result to identify the faulty interconnections of the target interposer. Experimental results show our method is both effective and efficient with achieving 100% fault coverage for all interposers. With scaling to more than hundreds of hundreds interposers, our method is still effective within two to three hours.
A Low-Power Analog-to-Digital Converter with Digitalized Amplifier for PAM Systems
(2014)
Ho, Yingchieh
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Kuo, Chou-Ming
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Su, ChauChin
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
In this paper, we have proposed a 4-bit 5-GSample/s flash analog-to-digital converter (ADC) for pulse amplitude modulation (PAM) systems. In order to achieve low-power consumptions, digitalized cells for analogue amplifying are developed in the proposed ADC. Digitalized cells reduce power significantly due to using fewer devices as compared to pure analogue designs. A self-biasing circuit is used in the digitalized amplifier can enhance linear amplifying region. Besides, the digitalized amplifier can achieve high speed according to its bandwidth compensation technique. The test chip is implemented with 90nm CMOS Logic and Mixed-Mode 1P9M Low-K Process. The low-power digitalized ADC is operated under 5GSample/s. All the results of post-simulation are demonstrated in a 16-PAM system, and efficient number of bit is 3.9bit. Moreover, INL and DNL are less than 0.5LSB. The power consumption of the ADC is 33.7mW, and the FoM of energy per conversion step is only 0.45pJ. The overall chip area is 0.873mm(2).
A Near-Threshold 480 MHz 78 mu W All-Digital PLL With a Bootstrapped DCO
(2013-11-01)
Ho, Yingchieh
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Yang, Yu-Sheng
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Chang, ChiaChi
;
Su, Chauchin
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交大名義發表
This paper presents a near-threshold low-power all-digital PLL (ADPLL). It includes a 9-bit bootstrapped DCO (BDCO) to reduce supply voltage and power consumption, a weighted thermometer-controlled resistor network (WTRN) to achieve high linearity, and a 4-bit sigma-delta modulator to improve the resolution through dithering. The ADPLL is fabricated in a 90 nm SPRVT low-K CMOS process with a core area of 0.057 mm(2). The measured results demonstrate that the bootstrapped ring oscillator (BTRO) oscillates at 602 MHz under a supply of 0.5 V and consumes 49.1 mu W. The ADPLL operates at 480 MHz (48 MHz) with a power consumption of 78 mu W (2.4 mu W) under a supply voltage of 0.5 V (0.25 V).
Cumulative Differential Non linearity Testing of ADCs
(2012-10-01)
Chen, Hungkai
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Ho, Yingchieh
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Su, Chauchin
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電控工程研究所
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Institute of Electrical and Control Engineering
This paper proposes a cumulative DNL (CDNL) test methodology for the BIST of ADCs. It analyzes the histogram of the DNL of a predetermined k LSBs distance to determine the DNL and gain error. The advantage of this method over others is that the numbers of required code bins and required samples are significantly reduced. The simulation and measurements of a 12-bit ADC show that the proposed CDNL has an error of less than 5% with only 2(12) samples, which can only be achieved with 2(22) samples using the conventional method. It only needs 16 registers to store code bins in this experiment.
Design of a Micro-Electrode Cell for Programmable Lab-on-CMOS Platform
(2016)
Ho, Yingchieh
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Wang, Gary
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Lai, Kelvin Yi-Tse
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Lug, Yi-Wen
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Liu, Keng-Ming
This paper presents a programmable lab-on-CMOS (LoCMOS) with micro-electrode cell array. Array structure is suitable for programmable like CMOS VLSIs. In order to improve the utilization, each micro-electrode cell is composed of actuation and sensing circuit. In addition, a CMOS-compatible extended drain MOSFET (EDMOS) is adopted under a 3V supply. This LoCMOS platform is composed of 1,800 microelectrodes with exploiting EDMOS to enable droplet actuations. Through its field programmability, the chip can successfully perform all microfluidic operations, droplet moving/cutting/mixing on a 2-dimenional microelectrode cell array. Implemented in 0.35um standard CMOS process, the LoCMOS platform demonstrates microfluidic functions and droplet detection. Measured results show successfully for actuation and real-time droplet location sensing.
Design of a Subthreshold-Supply Bootstrapped CMOS Inverter Based on an Active Leakage-Current Reduction Technique
(2012-01-01)
Ho, Yingchieh
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Chang, Chiachi
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Su, Chauchin
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電機工程學系
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電控工程研究所
This brief presents a bootstrapped CMOS inverter operated with a subthreshold power supply. In addition to improving the driving ability, a large gate voltage swing from - V-DD to 2V(DD) suppresses the subthreshold leakage current. As compared with other reported works, the proposed bootstrapped inverter uses fewer transistors operated in the subthreshold region. Therefore, our design has shorter delay time. The Monte Carlo analysis results indicate that a sigma of delay time is only 6.3 ns under the process and temperature variations with 200-mV operation. Additionally, a test chip is fabricated in the 90-nm SPRVT low-K CMOS process. Chip measurement results demonstrate the feasibility of operating ten-stage bootstrapped inverters with a 200-fF loading of each stage at 200-mV V-DD. The test chip is able to achieve 10-MHz clock rate at 200 mV V-DD, the power consumption is 1.01 mu W, and the leakage power is 107 nW.
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers
(2012-06-01)
Ho, Yingchieh
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Chen, Hung-Kai
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Su, Chauchin
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電機工程學系
;
電控工程研究所
This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ).
Energy-Effective Sub-Threshold Interconnect Design Using High-Boosting Predrivers
(2012-06-01)
Ho, Yingchieh
;
Chen, Hung-Kai
;
Su, Chauchin
;
電子工程學系及電子研究所
;
電控工程研究所
This paper investigates the performance of the interconnects with repeater insertion in the subthreshold region. A 3X complementary metal-oxide-semiconductor (CMOS) predriver and a 4X one are proposed to enhance the driving capability. As compared to the conventional repeater, the proposed ones have higher energy efficiency. In addition, the results of Monte Carlo analysis indicate that the propose predrivers have higher concentration under the process and temperature variation than conventional one at 0.15 V. A test chip with 3X and 4X predrivers for 10-mm on-chip bus has been fabricated in 65 nm SPRVT CMOS process. The measured results show that the 3X (4X) predrivers can achieve 5 Mb/s (1.5 Mb/s) data rate at 0.15 V with an efficiency of 35.2 fJ (32.8 fJ).
Evaluation and Verification of Channel Transmission Characteristics of Human Body for Optimizing Data Transmission Rate in Electrostatic-Coupling Intra Body Communication System: A Comparative Analysis
(2016-02-11)
Tseng, Yuhwai
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Su, Chauchin
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Ho, Yingchieh
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電控工程研究所
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Institute of Electrical and Control Engineering
Background Intra-body communication is a new wireless scheme for transmitting signals through the human body. Understanding the transmission characteristics of the human body is therefore becoming increasingly important. Electrostatic-coupling intra-body communication system in a ground-free situation that integrate electronic products that are discretely located on individuals, such as mobile phones, PDAs, wearable computers, and biomedical sensors, are of particular interest. Materials and Methods The human body is modeled as a simplified Resistor-Capacitor network. A virtual ground between the transmitter and receiver in the system is represented by a resister-capacitor network. Value of its resistance and capacitance are determined from a system perspective. The system is characterized by using a mathematical unit step function in digital baseband transmission scheme with and without Manchester code. As a result, the signal-to-noise and to-intersymbol-interference ratios are improved by manipulating the load resistor. The data transmission rate of the system is optimized. A battery-powered transmitter and receiver are developed to validate the proposal. Results A ground-free system fade signal energy especially for a low-frequency signal limited system transmission rate. The system transmission rate is maximized by simply manipulating the load resistor. Experimental results demonstrate that for a load resistance of 10k-50k Omega, the high-pass 3 dB frequency of the band-pass channel is 400kHz-2MHz in the worst-case scenario. The system allows a Manchester-coded baseband signal to be transmitted at speeds of up to 20M bit per second with signal-to-noise and signal-to-intersymbol-interference ratio of more than 10 dB. Conclusion The human body can function as a high speed transmission medium with a data transmission rate of 20Mbps in an electrostatic-coupling intra-body communication system. Therefore, a wideband signal can be transmitted directly through the human body with a good signal-to-noise quality of 10 dB if the high-pass 3 dB frequency is suitably selected.
Field-programmable lab-on-a-chip based on microelectrode dot array architecture
(2014-09-01)
Wang, Gary
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Teng, Daniel
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Lai, Yi-Tse
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Lu, Yi-Wen
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Ho, Yingchieh
The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called 'microelectrode cell', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 x 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.
Field-programmable lab-on-a-chip based on microelectrode dot array architecture
(2014-09-01)
Wang, Gary
;
Teng, Daniel
;
Lai, Yi-Tse
;
Lu, Yi-Wen
;
Ho, Yingchieh
The fundamentals of electrowetting-on-dielectric (EWOD) digital microfluidics are very strong: advantageous capability in the manipulation of fluids, small test volumes, precise dynamic control and detection, and microscale systems. These advantages are very important for future biochip developments, but the development of EWOD microfluidics has been hindered by the absence of: integrated detector technology, standard commercial components, on-chip sample preparation, standard manufacturing technology and end-to-end system integration. A field-programmable lab-on-a-chip (FPLOC) system based on microelectrode dot array (MEDA) architecture is presented in this research. The MEDA architecture proposes a standard EWOD microfluidic component called \'microelectrode cell\', which can be dynamically configured into microfluidic components to perform microfluidic operations of the biochip. A proof-of-concept prototype FPLOC, containing a 30 x 30 MEDA, was developed by using generic integrated circuits computer aided design tools, and it was manufactured with standard low-voltage complementary metal-oxide-semiconductor technology, which allows smooth on-chip integration of microfluidics and microelectronics. By integrating 900 droplet detection circuits into microelectrode cells, the FPLOC has achieved large-scale integration of microfluidics and microelectronics. Compared to the full-custom and bottom-up design methods, the FPLOC provides hierarchical top-down design approach, field-programmability and dynamic manipulations of droplets for advanced microfluidic operations.
High-R Poly Resistance Deviation Improvement From Suppressions of Back-End Mechanical Stresses
(2017-10-01)
Lin, Tingyou
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Ho, Yingchieh
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Su, Chauchin
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電機工程學系
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電信工程研究所
This paper investigates techniques for N-type high-resistance polysilicon resistors to reduce the resistance deviation which is caused by the back-end mechanical stress. In the back-end layers of the wafer, a top metal thickness equal to 3 mu m is provided to increase the heat allowing current density in the metal routes of power ICs. The top metal processing yields the mechanical stress to increase the resistance by the piezoresistance effect. To eliminate the mechanical stresses, a new layout is proposed with the full passivation cutting (FPC). The resistor with an FPC uses the passivation film separation to create a physical empty room for suppressing the mechanical stresses on the polysilicon. The proposed layout has been verified in the 0.4-mu m bipolar-CMOS-DMOS process, and the resistance shifts were compared with other four-type layouts. Compared to those original layouts, the proposed layout exhibits the improvements in the resistance deviation reduction in the maximum ratio 20.80%.
LDMOS Channel Thermometer Based on a Thermal Resistance Sensor for Balancing Temperature in Monolithic Power ICs
(2017-06-01)
Lin, Tingyou
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Ho, Yingchieh
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Su, Chauchin
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電子工程學系及電子研究所
;
電信工程研究所
This paper presents a method of thermal balancing for monolithic power integrated circuits (ICs). An on-chip temperature monitoring sensor that consists of a poly resistor strip in each of multiple parallel MOSFET banks is developed. A temperature-to-frequency converter (TFC) is proposed to quantize on-chip temperature. A pulse-width-modulation (PWM) methodology is developed to balance the channel temperature based on the quantization. The modulated PWM pulses control the hottest of metal-oxide-semiconductor field-effect transistor (MOSFET) bank to reduce its power dissipation and heat generation. A test chip with eight parallel MOSFET banks is fabricated in TSMC 0.25 mu m HV BCD processes, and total area is 900 x 914 mu m(2). The maximal temperature variation among the eight banks can reduce to 2.8 degrees C by the proposed thermal balancing system from 9.5 degrees C with 1.5 W dissipation. As a result, our proposed system improves the lifetime of a power MOSFET by 20%.