Browsing by Author "Hsiao, Chien-Nan"

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Characteristics of atomic-layer-deposited Al(2)O(3) high-k dielectric films grown on Ge substrates
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Liu, Jun-Cheng
;
Kei, Chi-Chung
This paper describes the structural and electrical properties of Al(2)O(3) thin films grown through atomic layer deposition onto Ge substrates over a wide deposition temperature range (50-300 degrees C). From grazing-incidence X-ray reflectivity and X-ray photoelectron spectroscopy, we found that increasing the deposition temperature improved the Al(2)O(3) film density and its dielectric stoichiometry; nevertheless, dielectric intermixing between main Al(2)O(3) and interfacial GeO(2) appeared at temperatures above 200 degrees C, along with degradation of the GeO(2)/Ge interface. Accordingly, a relatively large gate leakage current (J(g)) and a high density of interfacial states D(it) (> 10(13) cm(-2) eV(-1)) were observed as a result of deterioration of the entire Al(2)O(3)/Ge structure at higher deposition temperatures. In addition, although subsequent high-temperature processing at 600 degrees C in a N(2) ambient could relieve the oxygen-excessive behavior further, i.e., to provide a more stoichiometric film, the accompanying GeO(x) volatilization close to the dielectric interface caused greater damage to the electrical performance. Only forming gas annealing (H(2)/N(2), 1:10) at low temperature (300 degrees C) improved the capacitance-voltage characteristics of the Pt/Al(2)O(3)/Ge structure, in terms of providing a lower value of D(it) (ca. 6 x 10(11) cm(-2) eV(-1)), a lower value of J(g), and a reduced hysteresis width.
Effect of In/Al ratios on structural and optical properties of InAlN films grown on Si(100) by RF-MOMBE
(2014-05-01)
Chen, Wei-Chun
;
Wu, Yue-Han
;
Peng, Chun-Yen
;
Hsiao, Chien-Nan
;
Chang, Li
InxAl1-xN films were deposited on Si(100) substrate using metal-organic molecular beam epitaxy. We investigated the effect of the trimethylindium/trimethylaluminum (TMIn/TMAI) flow ratios on the structural, morphological, and optical properties of InxAl1-xN films. Surface morphologies and microstructure of the InxAl1-xN films were measured by atomic force microscopy, scanning electron microscopy, X-ray diffraction (XRD), and transmission electron microscopy (TEM), respectively. Optical properties of all films were evaluated using an ultraviolet/visible/infrared (UV/Vis/IR) reflection spectrophotometer. XRD and TEM results indicated that InxAl1-xN films were preferentially oriented in the c-axis direction. Besides, the growth rates of InxAl1-xN films were measured at around 0.6 mu m/h in average. Reflection spectrum shows that the optical absorption of the InxAl1-xN films redshifts with an increase in the In composition.
Effects of interfacial sulfidization and thermal annealing on the electrical properties of an atomic-layer-deposited Al(2)O(3) gate dielectric on GaAs substrate
(2008-04-01)
Cheng, Chao-Ching
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Chien, Chao-Hsin
;
Luo, Guang-Li
;
Yang, Chun-Hui
;
Chang, Ching-Chih
In this study we investigated the interfacial chemistry occurring between an atomic-layer-deposited Al(2)O(3) high-k film and a GaAs substrate and the impact of sulfidization and thermal annealing on the properties of the resultant capacitor. We observed that sulfide passivation of the Al(2)O(3)/GaAs structure improved the effect of Fermi level pinning on the electrical characteristics, thereby providing a higher oxide capacitance, smaller frequency dispersion, and reduced surface states, as well as decreased interfacial charge trapping and gate leakage currents. Photoemission analysis indicated that the (NH(4))(2)S-treated GaAs improved the quality of the as-deposited Al(2)O(3) thin film and preserved the stoichiometry of the dielectric during subsequent high-temperature annealing. This behavior was closely correlated to the diminution of GaAs native oxides and elemental arsenic defects and their unwanted diffusion. In addition, thermal processing under an O(2) atmosphere, relative to that under N(2), decreased the thickness of the Al(2)O(3) gate dielectric and relieved the gate leakage degradation induced by metallic arsenic; as a result, superior dielectric reliability was attained. We discuss the underlying thermochemical reactions that account for these experimental observations. (C) 2008 American Institute of Physics.
Effects of Minority-Carrier Response Behavior on Ge MOS Capacitor Characteristics: Experimental Measurements and Theoretical Simulations
(2009-05-01)
Cheng, Chao-Ching
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Chien, Chao-Hsin
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Luo, Guang-Li
;
Ling, Yu-Ting
;
Chang, Ruey-Dar
In this paper, we present MEDICI simulations of the admittance-voltage properties of Ge and Si MOS devices, including analyses of substrate conductance Grub and high-low transition frequency f(tran), to explore the differences in the minority-carrier response. The Arrhenius-dependent G(sub) characteristics revealed that a larger energy loss-by at least four orders of magnitude-occurs in Ge than in Si, reflecting the fast minority-carrier response rate, i.e., a higher value of f(tran). We confirmed that the higher intrinsic carrier concentration in Ge, through the generation/recombination of midgap trap levels as well as the diffusion mechanism, resulted in the onset of low-frequency C-V curves in the kilohertz regime, accompanying the gate-independent inversion conductance. The experimental data obtained from Al(2)O(3)/Ge MOS capacitors were consistent with the values of G(sub) and f(tran) obtained from MEDICI predictions and theoretical calculations. In addition, upon increasing the inversion biases, we observed shifts in the G(sub/)f conductance peaks to low frequencies that mainly arose from the transition of minority carriers with bulk traps in the depletion layer. Meanwhile, we estimated that the bulky defects of ca. (2-4) x 10(15) cm(-3) exist in present-day low-doped Ge wafers.
Electrical and material characterization of atomic-layer-deposited Al(2)O(3) gate dielectric on ammonium sulfide treated GaAs substrates
(2008)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Chang, Ching-Chih
;
Kei, Chi-Chung
This paper has studied the electrical and interfacial properties of atomic-layerdeposited Al(2)O(3) thin film on ammonium-sulfide passivated GaAs. It was found that the Al(2)O(3) deposited at 300 degrees C relative to that at 100 degrees C showed the nearly four orders of magnitude reduction in gate leakage current at the capacitance-equivalent-thickness of 40 angstrom. The capacitance-voltage (C-V) characteristics displayed the higher oxide capacitance, reduced frequency dispersion and less charge trapping when GaAs receiving (NH(4))(2)S sulfide immersion; these improvements can be reasonably explained by the suppression of both native oxides and the resultant improved interface quality. Annealing as-deposited Al(2)O(3)/GaAs structures at high temperatures further reduces the Fermi level pinning effect on accumulation capacitance, however, causes an increase in C-V frequency dispersion and gate leakage current. We suggested that these phenomena are strongly associated to the amount of As-related defects resided at the dielectric/ substrate interface during thermal desorption.
Epitaxial Germanium on SOI Substrate and Its Application of Fabricating High I-ON/I-OFF Ratio Ge FinFETs
(2013-06-01)
Chung, Cheng-Ting
;
Chen, Che-Wei
;
Lin, Jyun-Chih
;
Wu, Che-Chen
;
Chien, Chao-Hsin
Integrating germanium (Ge) thin film on silicon-on-insulator (SOI) substrate and fabricating Ge fin field-effect transistors (FinFETs) are demonstrated in this paper. Directly grown Ge film on a high-resistivity thin SOI substrate provides a good platform for fabricating advanced Ge devices. The SOI structure could effectively suppress junction leakage; therefore, high I-ON/I-OFF ratio (similar to 5 x 10(5), at V-D = 0.1 V) of the drain current is achieved. Tri-gate structure provides better short-channel control abilities for the Ge FinFETs, and the drain-induced barrier lowering and threshold voltage (V-TH) shift can be maintained at the level of similar to 110 mV/V and similar to 0.1 V, respectively, for Ge n-channel FinFET with L-channel = 120 nm and W-Fin = 40 nm. Multifin Ge FinFET with L-channel = 170 nm and W-Fin = 50 nm is also illustrated. Both N-and P-FinFETs possess high I-ON/I-OFF ratio over 104. Besides, the subthreshold swing could be reduced around 25% after forming gas annealing.
Experimental Demonstration of (111)-Oriented GaAs Metal-Oxide-Semiconductor Field-Effect-Transistors with Hetero-Epitaxial Ge Source/Drain
(2014)
Han, Tsung-Yu
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Luo, Guang-Li
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Cheng, Chao-Ching
;
Ko, Chih-Hsin
;
Wann, Clement H.
We demonstrate source/drain (S/D) design for GaAs n-type metal-oxide-semiconductor field-effect transistor (NMOSFET) by embedding Ge into recessed S/D region to eliminate the intrinsic issues of the low solid solubility of dopants and low density of states (DOS) in GaAs material. For achieving high quality S/D epitaxy, the effects of substrate orientation and surface preparation on the quality of the epitaxial Ge film were investigated. High quality Ge film was successfully grown on the GaAs (111)A substrate by using a ultra high vacuum chemical vapor deposition (UHVCVD) tool and the significant improvement in the surface root-mean-square (RMS) roughness was observed as compared to that on the (100) substrate. The fabricated GaAs NMOSFET with hetero-Ge S/D exhibits an I-on/I-off ratio of similar to 2.5 x 10(2). Even though the performance can be further improved, we think our proposed scheme sheds the light on overcoming the issues of the low solid solubility of n-dopant and low DOS in III-V MOSFETs. (C) 2014 The Electrochemical Society. All rights reserved.
Five-element circuit model using linear-regression method to correct the admittance measurement of metal-oxide-semiconductor capacitor
(2009-01-01)
Cheng, Chao-Ching
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Chien, Chao-Hsin
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Luo, Guang-Li
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Liu, Jun-Cheng
;
Chen, Yi-Cheng
The authors present a linear-regression method based on a five-element circuit model to correct measured capacitance-voltage and conductance-voltage curves. This model explains the effects of series resistance and parasitic capacitance/inductance on the frequency dispersion of measured capacitance and the magnification of measured conductance. These extracted parasitic components show significant dependencies on the geometry of capacitor structure, thereby causing different frequency-dependent capacitance characteristics in measurements. (C) 2009 American Vacuum Society. [DOI: 10.1116/1.3058724]
Heteroepitaxial growth of InN on GaN intermediate layer by PA-MOMBE
(2011-07-01)
Lai, Fang-I
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Kuo, Shou-Yi
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Chen, Wei-Chun
;
Lin, Woei-Tyng
;
Wang, Wei-Lin
In this paper, high-quality wurtzite indium nitride was epi-grown on sapphire substrates by plasma-assisted metal-organic molecule beam epitaxy system (PA-MOMBE). Structural and electrical properties of the InN films were significantly improved by employing a GaN buffer layer. In addition, high-resolution X-ray diffraction, field emission scanning electron microscopy, transmission electron microscopy (TEM), Hall Effect, Raman and photoluminescence spectroscopy were carried out to characterize the effect of the growth temperature on structural and optoelectronic properties. It was found that highly c-axis oriented InN epilayer can be obtained by optimizing growth conditions. TEM images reveal that the epitaxially grown InN/GaN interface is sharp, and the spacing of the InN(0 0 0 2) lattice plane is about 0.57 nm. Raman spectra also show a sharp peak at 491 cm(-1) attributed to the E(2)(high) mode of wurtzite InN. These results indicate that the improvement of InN material quality can be achieved using heteroepitaxy on GaN/sapphire templates. (C) 2011 Elsevier B.V. All rights reserved.
Improved stress reliability of analog TiHfO metal-insulator-metal capacitors using high-work-function electrode
(2007-11-01)
Cheng, Chun-Hu
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Chiang, Kuo-Cheng
;
Pan, Han-Chang
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Hsiao, Chien-Nan
;
Chou, Chang-Pin
We have studied the reliability of high-K (K similar to 49) TixHf1-xO (x similar to 0.67) metal-insulator-metal (MIM) capacitors after constant voltage stress induction. The use of a high-work-function Ni top electrode improves not only the leakage current, and temperature- and voltage-coefficients of capacitance, but also the long-term capacitance variation after stress induction.
Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al(2)O(3) Gate Dielectric
(2009-08-01)
Cheng, Chao-Ching
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Chien, Chao-Hsin
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Luo, Guang-Li
;
Lin, Ching-Lun
;
Chen, Hung-Sen
In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-Al(2)O(3) gate dielectrics. The magnitudes of the rectifying ratios for the Ge p(+)-n and n(+)-p junctions exceeded three and four orders of magnitude (in the voltage range of +/-1 V), respectively, with accompanying reverse leakages of ca. 10(-2) and 10(-4) A . cm(-2), respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 degrees C boosted the device on-current, decreased the Al(2)O(3)/Ge interface states to 8 x 10(11) cm(-2) . eV(-1), and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm(2) . V(-1) . s(-1) and > 10(3), respectively, for the p-FET (W/L = 100 mu m/4 mu m), while these values were less than 100 cm(2) . V(-1) . s(-1) and ca. 10(3), respectively, for the n-FET (W/L = 100 mu m/9 mu m). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.
Junction and Device Characteristics of Gate-Last Ge p- and n-MOSFETs With ALD-Al2O3 Gate Dielectric
(2009-08-01)
Cheng, Chao-Ching
;
Chien, Chao-Hsin
;
Luo, Guang-Li
;
Lin, Ching-Lun
;
Chen, Hung-Sen
In this paper, we investigated the characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-Al2O3 gate dielectrics. The magnitudes of the rectifying ratios for the Ge p(+)-n and n(+)-p junctions exceeded three and four orders of magnitude (in the voltage range of +/-1 V), respectively, with accompanying reverse leakages of ca. 10(-2) and 10(-4) A . cm(-2), respectively. The site of the primary leakage path, at either the surface periphery or junction area, was determined by the following conditions: 1) the thermal budget during dopant activation, and 2) whether forming gas annealing (FGA) was employed or not. In addition, performing FGA at 300 degrees C boosted the device on-current, decreased the Al2O3/Ge interface states to 8 x 10(11) cm(-2) . eV(-1), and improved the reliability of bias temperature instability. The peak mobility and on/off ratio reached as high as 225 cm(2) . V-1 . s(-1) and > 10(3), respectively, for the p-FET (W/L = 100 mu m/4 mu m), while these values were less than 100 cm(2) . V-1 . s(-1) and ca. 10(3), respectively, for the n-FET (W/L = 100 mu m/9 mu m). The relatively inferior n-FET performance resulted from the larger source/drain contact resistance, higher surface states scattering, and lower substrate-doping concentration.
The study of compensative structure assisted convex and concave corner structures etching by Inductively Coupled Plasma-Reactive Ion Etch (ICP-RIE)
(2015)
Lin, Yu-Hsin
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Cheng, Yuan-Chieh
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Chu, Nien-Nan
;
Hsu, Wensyang
;
Tang, Yu-Hsiang
In this paper, the compensative structure assisted the convex and concave corner structures etch in inductively coupled plasma reactive ion etch (ICP-RIE) have been studied. In anisotropic silicon etching, under the Bosch patent, sequentially alternating etch and passivation cycles can easily achieve high aspect ratio silicon structures. But, the feature size of the convex and concave corner structures are difficult to maintain as original design at the bottom position in deep etch, due to non-vertical movement plasma etch. A compensative structure can obstruct the non-vertical plasma to etch the convex corner structures and reduce the etch lag effect during the etch process leading to better profile at deep etch. The current study systematically investigates plasma condition to verify feasibility of the proposed method, and discusses effect of the gap between compensative structure and convex and concave corner structures at three different gaps of 15, 10, 5 mu m. It demonstrate the compensative structure with small gap in front of the convex and concave corner structures have better profile at deep ICP-RIE etching.