Browsing by Author "Hsueh, Fu-Kuo"

Now showing 1 - 20 of 30

32-nm Multigate Si-nTFET With Microwave-Annealed Abrupt Junction
(2016-05)
Hou, Fu-Ju
;
Sung, Po-Jung
;
Hsueh, Fu-Kuo
;
Wu, Chien-Ting
;
Lee, Yao-Jen
Microwave annealing (MWA) activates dopants through solid-phase epitaxial regrowth with low thermal budget. Optimizing the microwave power during MWA is capable of realizing low defect density at the junction, suppressing the dopant diffusion, and mitigating the straggle effect of ion implantation. These favorable features of MWA facilitate the formation of extremely abrupt junction profiles in tunnel FETs (TFETs). In conjunction with the improved gate-to-channel controllability of the multiple-gate (MG) structure, we demonstrate high-performance lateral n-type Si-TFETs using a CMOS-compatible process flow with excellent band-to-band tunneling efficiency and device scalability. The 32-nm MG Si-TFET shows promising characteristics, including a high ON-state current of 41.3 mu A/mu m, a large current ON/OFF ratio of > 5 x 10(7), and minimal short-channel effect using V-G = 2 V and V-D = 1 V.
3D 65nm CMOS with 320 degrees C Microwave Dopant Activation
(2009)
Lee, Yao-Jen
;
Lu, Yu-Lun
;
Hsueh, Fu-Kuo
;
Huang, Kuo-Chin
;
Wan, Chia-Chen
For the first time, CMOS TFTs of 65nm channel length have been demonstrated by using a novel microwave dopant activation technique. A low temperature microwave anneal is. demonstrated and discussed in this study. We have successfully activated the poly-Si gate electrode and source/drain junctions, BF2 for p-MOS TFTs and P-31 for n-MOS TFTs at a low temperature of 320 degrees C without diffusion. The technology is promising for high performance and low cost upper layer nanometer-scale transistors as required by low temperature 3D-ICs fabrication.
A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication
(2011-11-01)
Chen, Hou-Yu
;
Chen, Chun-Chi
;
Hsueh, Fu-Kuo
;
Liu, Jan-Tsai
;
Shy, Shyi-Long
For more than 45 years, photon-and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 mu m(2)), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V(dd) regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.
Amorphous-Layer Regrowth and Activation of P and As Implanted Si by Low-Temperature Microwave Annealing
(2011-07-01)
Hsueh, Fu-Kuo
;
Lee, Yao-Jen
;
Lin, Kun-Lin
;
Current, Michael I.
;
Wu, Ching-Yi
Microwave annealing of dopants in Si has been reported to produce highly activated junctions at temperatures far below those needed for comparable results using conventional thermal processes. However, the details of the kinetics and mechanisms for microwave annealing are far from well understood. In this paper, 20-keV arsenic (As) and 15-keV phosphorus (P) implants, in a dose range from 1 to 5 x 10(15) ion/cm(2), were annealed by microwave methods at temperatures below 500 degrees.C. These junctions were characterized by profile studies with secondary ion mass spectrometry and spreading resistance profiling, sheet resistance with four-point probe, and extensive use of cross-sectional transmission electron microscopy to follow the regrowth of the as-implanted amorphous layers created by the implantation. The amorphous-layer regrowth was observed to be uneven in time, with relatively little amorphous/crystalline interface motion for less than 50 s, followed by rapid regrowth for longer times. Sheet resistance values continued to drop for anneal times after the regrowth process was complete, with some evidence of dopant deactivation for anneal times of 600 s.
Analog and RF Characteristics of Power FinFET Transistors With Different Drain-Extension Designs
(2018-10-01)
Chen, Bo-Yuan
;
Chen, Kun-Ming
;
Chiu, Chia-Sung
;
Huang, Guo-Wei
;
Chen, Hsiu-Chih
Analog and RF characteristics of power FinFET transistors with different drain-extension structures are investigated for microwave integrated circuit applications. The power FinFETs were designed based on the drain-extended MOSFET structure and fabricated using a standard low-voltage FinFET process. Three various drain-extension configurations are demonstrated and compared. With the low-doped drain extension, the breakdown voltage of power FinFETs is higher than 6.5 V for all samples. For standard power devices, where the drain extension is performed with narrow fins, a high drain resistance is inevitable, resulting in high on-resistance and poor analog and RF performances. For devices with wide drain-extension fins (wide drain FinFET) or a planar drain extension (hybrid FinFET), lower drain resistances are obtained owing to the larger extension width. Therefore, the on-resistances of the wide drain and hybrid devices are much lower than that of the standard counterpart. Moreover, these devices with modified drain extensions also exhibit better analog and RF behaviors. The cutoff frequency of power FinFETs is boosted from 30 to 53 GHz when the drain extension is changed from narrow fins to a planar layout. These experimental results indicate that RF power FinFETs with good performance would be realized with the modified drain-extension designs.
Characterization of Ultra-Thin Ni Silicide Film by Two-Step Low Temperature Microwave Anneal
(2014)
Wu, Chien-Ting
;
Lee, Yao-Jen
;
Hsueh, Fu-Kuo
;
Sung, Po-Jung
;
Cho, Ta-Chun
A novel silicide process with two-step low temperature microwave annealing (MWA) achieves NiSi thickness of 10 nm while maintaining low resistance, and an ultra-thin Ni silicide film, only 4.5 nm, has been realized. In this MWA system, we insert quartz and Si susceptors to change the absorption efficiency of the process wafer and provide fine turning in temperature control during annealing. The thickness of NiSi film is determined by microwave power and by changing the number and the position of quartz and Si susceptors in the first step of the anneal process. The STEM-HAADF combined EELS/EDS spectroscopies are used to analyze the electronic excitations and identify the phase of Ni silicide. (C) 2014 The Electrochemical Society. [DOI: 10.1149/2.006405jss] All rights reserved.
Comparisons on performance improvement by nitride capping layer among different channel directions nMOSFETs
(2007)
Tsai, Tzu-, I
;
Lee, Yao-Jen
;
Chen, King-Sheng
;
Wang, Jeff
;
Hsueh, Fu-Kuo
DC and high-frequency characteristics of trigate polycrystalline-silicon thin-film transistors with different layout geometries
(2019-04-01)
Chen, Bo-Yuan
;
Chen, Kun-Ming
;
Shiao, Yu-Shao Jerry
;
Lin, Chuang-Ju
;
Huang, Guo-Wei
In this paper, we present the dc and high-frequency characteristics of trigate polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) for RF applications. Trigate TFTs were fabricated using a 3D-IC process and designed with a multi-finger gate and multi-channel configuration. To obtain an optimal device design guideline, different source/drain (S/D) extension dimensions and channel layouts are investigated. We find that devices with a shorter or wider extension have higher cutoff frequencies (f(T)) and maximum oscillation frequencies (f(max)) owing to their lower S/D resistances. In addition, the high-frequency performance can be further improved by adopting the tapered channel structure, where the channel width increases gradually from the source to the drain. For the optimal device designs, the values of f(T) and f(max) are around 25 GHz and 30 GHz, respectively. The high f(T) and f(m)(ax) as well as excellent gate controllability in our devices indicate the trigate poly-Si TFT could be a suitable candidate for low-cost RFIC applications. (C) 2019 The Japan Society of Applied Physics
Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology
(2015)
Lee, Yao-Jen
;
Hou, Fu-Ju
;
Chuang, Shang-Shiun
;
Hsueh, Fu-Kuo
;
Kao, Kuo-Hsing
We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.
Dopant Activation in Single-Crystalline Germanium by Low-Temperature Microwave Annealing
(2011-02-01)
Lee, Yao-Jen
;
Chuang, Shang-Shiun
;
Hsueh, Fu-Kuo
;
Lin, Ho-Ming
;
Wu, Shich-Chuang
Phosphorus activated in germanium epitaxy atop Si wafer by low-temperature microwave annealing technique was investigated in this letter. Compared to the conventional RTA process, the temperature of phosphorus activation could be 120 degrees C to 140 degrees C which is an improvement in temperature reduction at the same sheet resistance. According to the SRP, up to 150 degrees C reduction in maximum temperature at the same activation concentration (about 2 x 10(19) cm(-3)) could be achieved. Through adjusting the microwave power and process time, sheet resistance could be decreased while suppressing dopant diffusion. In addition, the inserted susceptor wafers above and below the processing wafer also suppressed the dopant diffusion and improved film roughness.
Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter
(2020-01-01)
Sung, Po-Jung
;
Su, Chun-Jung
;
Lo, Shih-Hsuan
;
Hsueh, Fu-Kuo
;
Lu, Darsen D.
In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with I-D change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of I-d. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various V-D from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.
Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
(2020-09-01)
Sung, Po-Jung
;
Chang, Shu-Wei
;
Kao, Kuo-Hsing
;
Wu, Chien-Ting
;
Su, Chun-Jung
In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.
First Fully Functionalized Monolithic 3D(+) IoT Chip with 0.5 V Light-electricity Power Management, 6.8 GHz Wireless-communication VCO, and 4-layer Vertical ReRAM
(2016-01-01)
Hsueh, Fu-Kuo
;
Shen, Chang-Hong
;
Shieh, Jia-Min
;
Li, Kai-Shin
;
Chen, Hsiu-Chih
For the first time, we report low-cost heterogeneously integrated sub-40nm epi-like Si monolithic internet of thins (IoT) 3D(+)-IC with wireless communication, light-electricity power management and vertical ReRAM (VRRAM) modules. High current driving multi-channel 3D(+) UTB-MOSFETs (600 mu A/282 mu A@V-G = +/- 1V for 10-channel P/N FETs) was fabricated by low thermal budget super-CMP-planarized visible laser-crystallized epi-like Si channel and CO2 far-infrared laser annealing (CO2-FIR-LA) activation technologies that support a 6.8GHz high frequency VCO circuits, 0.5V low-voltage power management circuit and drives 20nm 4-layer VRRAM (Set/Reset <1.2V/1.8V, 3-bits/cell). This unique TSV-free monolithic 3D(+)IC process provides the superiority in 3D hetero-integration; we successfully integrate these circuits in a low cost, small footprint, fully functionalized 3D(+) IoT chip.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
;
Cho, Ta-Chun
;
Sung, Po-Jung
;
Kao, Kuo-Hsing
;
Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
High Tensile Stress with Minimal Dopant Diffusion by Low Temperature Microwave Anneal
(2011)
Lee, Yao-Jen
;
Lu, Yu-Lun
;
Mu, Zheng-Chang
;
Hsueh, Fu-Kuo
;
Chao, Tien-Sheng
In this letter, rapid thermal annealing (RTA) and microwave annealing (MA) are compared to demonstrate the dopant activation. Using microwave annealing, the dopant in the Si was well-activated and showed suppressed dopant diffusion, as compared to traditional high temperature RTA. In addition, SiN(x) films after low temperature MA treatment presented higher tensile stress than the films annealed by RTA. Therefore, this MA approach could potentially be applied to these behaviors of I distribution and higher tensile stress SiNx film may be useful in contact etch-stop layer or stress memorization technique in the fabrication of small pitch nanoscaled n-channel Metal-Oxide-Semiconductor Field Effect Transistors. (C) 2011 The Electrochemical Society. [DOI: 10.1149/1.3536462] All rights reserved.
High-Performance Uniaxial Tensile Strained n-Channel JL SOI FETs and Triangular JL Bulk FinFETs for Nanoscaled Applications
(2017-05-01)
Sung, Po-Jung
;
Cho, Ta-Chun
;
Hou, Fu-Ju
;
Hsueh, Fu-Kuo
;
Chung, Sheng-Ti
In this paper, one proposed an effective method to enhance current drivability of junctionless FETs (JL-FETs) by utilizing uniaxial tensile strain effects. The strained layers were deposited on JL-FETs on silicon-on-insulator (SOI) and bulk Si wafers, respectively. Strained JL SOI FETs show an extremely low subthreshold swing (S. S.) of 65 mV/decade with ION/IOFF > 10(9); strained JL bulk FinFETs show an S. S. of 75 mV/decade with I-ON/I-OFF > 10(7). For strained JL bulk FinFETs, a triangular fin shape could suppress leakage current effectively. Regardless of substrates, JL FETs showed excellent performance owing to uniaxial tensile strain technology. Analysis of leakage current in strained JL FETs included effects on Gate-induced drain leakage trap-assisted tunneling effects were discussed by ID-VG curves under various temperatures and activation energy. Compared with JL SOI gate-all-around structures, JL bulk FinFET possesses higher ID and offer the promise of higher integration flexibility for Si CMOS compatible process for the future applications.
Impacts of a buffer layer and hi-wafers on the performance of strained-channel NMOSFETs with SiN capping layer
(2007)
Tsai, Tzu-, I
;
Lee, Yao-Jen
;
Chen, King-Sheng
;
Wang, Jeff
;
Wan, Chia-Chen
Impacts of a buffer layer and hydrogen-annealed wafers on the performance of strained-channel nMOSFETs with SiN-capping layer
(2008-10-01)
Tsai, Tzu-I
;
Lin, Horng-Chih
;
Lee, Yao-Jen
;
Chen, King-Sheng
;
Wang, Jeff
In this study, the effects of Si3N4 layer capping and TEOS buffer layer inserted prior to the Si3N4 deposition on the NMOS device characteristics as well as correlated hot-electron degradations were investigated. The devices were built on two kinds of the substrates, namely, Cz and hydrogen-annealed (Hi) wafers. More importantly, we found that hydrogen species is the primary culprit for aggravated reliabilities in strained devices. By exerting the accelerated stress test, we could study the hot-electron degradation thoroughly in terms of threshold voltage shift (Delta V-TH), transconductance degradation (Delta Gm) and so on. The TEOS buffer layer could effectively block the diffusion of hydrogen species from the Si3N4 capping layer into the channel and the Si/SiO2 interface during the Si3N4 deposition as well as subsequent thermal cycles. (C) 2008 Elsevier Ltd. All rights reserved.
Low-Temperature Microwave Annealing for MOSFETs With High-k/Metal Gate Stacks
(2013-10-01)
Lee, Yao-Jen
;
Tsai, Bo-An
;
Lai, Chiung-Hui
;
Chen, Zheng-Yao
;
Hsueh, Fu-Kuo
In this letter, low-temperature (480 degrees C) microwave annealing (MWA) for MOS devices with high-k/metal gate-stacks is demonstrated. The capacitance-voltage (C-V) characteristics of the MOS gate-stacks, TiN/HfO2, and TaN/HfO2, after different annealing methods are discussed. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated using low temperature MWA. In addition, the short channel effects in nMOSFETs annealed by MWA can be also improved because of the suppression of dopant diffusion and stabilization of EOT.
Low-temperature Microwave Annealing Processes for Future IC Fabrication
(2014)
Lee, Yao-Len
;
Tsai, Bo-An
;
Cho, Ta-Chun
;
Hsueh, Fu-Kuo
;
Sung, Po-Jung
Low temperature microwave annealing (MWA) for IC processing is promising. In this study, using microwave annealing for dopant activation and thermal stability of the high-k/metal gate is investigated. Implanted species, such as phosphorus, arsenic, and boron, can also be well-activated and diffusionless in Si after microwave annealing. The flat band voltage shift of metal gate was suppressed due to the low temperature process. The increases in equivalent oxide thickness (EOT) of the MOS devices after dopant activation processing can be eliminated by using low temperature MW A. In addition, the short channel effects in n & pMOSFETs annealed by MW A can be also improved due to the suppression of dopant diffusion and stabilization of EOT.