Browsing by Author "Hu, Chenming"

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3D Ferroelectric-like NVM/CMOS Hybrid Chip by sub-400 degrees C Sequential Layered Integration
(2012-01-01)
Lien, Yu-Chung
;
Shieh, Jia-Min
;
Huang, Wen-Hsien
;
Hsieh, Wei-Shang
;
Tu, Cheng-Hui
For the first time, a sequentially processed 3D hybrid chip is demonstrated by stacking low-temperature (LT) Ferroelectric-like (FE-like) metal-oxide nonvolatile memory (NVM) and CMOS. The high-mobility (333 and 113 cm(2)/V-s) and low-subthreshold swing (97 and 112 mV/decade) N/P-type thin film transistors (TFTs) construct stacked inverters showing sharp transfer characteristic as the fundamental element of CMOS array and stacked 3D NVMs. The sequential layered integration is enabled by cutting-edge low thermal-budget plasma/laser processes and self-assembled FE-like metal-oxide materials. The implementation of sub-400 degrees C new-type metal-ion (Eu+3)-mediated atomic-polar-structured (Eu+3-APS) dielectric realizes stackable FE-like NVMs with program speed of 100 nanosecond, toward future 3D layered CMOS with giant high-speed dat-storage application era.
A Comprehensive Study of Ge1-xSix on Ge for the Ge nMOSFETs with Tensile Stress, Shallow Junctions and Reduced Leakage
(2009)
Luo, Guang-Li
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Huang, Shih-Chiang
;
Chung, Cheng-Ting
;
Heh, Dawei
;
Chien, Chao-Hsin
For the first time, growth of high-quality Ge-rich Ge1-xSix (0 <= x <= 0.14) layers on Ge substrate was demonstrated. An effective suppression of the phosphorus diffusion in Ge1-xSix and a better thermal stability of the nickel germanide on Ge1-xSix were observed. A higher rectifying ratio with a reduced diode leakage current in n(+)-Ge1-xSix/p-Ge1-xSix is compared with n(+)-Ge/p-Ge. These results indicate that it is suitable for Ge1-xSix to be used as source/drain (S/D) to fabricate the uniaxial tensile-strained channel Ge nMOSFETs.
A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
(2020-01-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.
A Novel Nanoinjection Lithography (NInL) Technology and Its Application for 16-nm Node Device Fabrication
(2011-11-01)
Chen, Hou-Yu
;
Chen, Chun-Chi
;
Hsueh, Fu-Kuo
;
Liu, Jan-Tsai
;
Shy, Shyi-Long
For more than 45 years, photon-and electron-sensitive materials have been used to produce pattern-transfer masks in the lithographic manufacturing of integrated circuits. With the semiconductor technology feature size continuing to shrink and the requirements of low-variability and low-cost manufacturing, optical lithography is driven to its limits. In this paper, we report a novel nanoinjection lithography (NInL) technique that employs electron-beam-assisted deposition to form pattern-transfer hard mask in a direct-write deposit approach. By scanning the 4.6-nm-diameter electron beam while injecting a suitable organometallic precursor gas around the location of e-beam and just above the substrate, we form a high-density (pitch: 40 nm) high-uniformity (3-sigma linewidth roughness: 2 nm) hard mask for subsequent etching without using proximity-effect correction techniques. Furthermore, this technique can also directly deposit a metal pattern for interconnect or a dielectric pattern without the need for separate metal or dielectric deposition, photoresist etch-mask, and etching processes. The NInL approach simplifies the hard-mask creation or even metal or dielectric pattern creation process modules from five or tens of steps to only a single step. Therefore, it saves both photomask making and wafer processing costs. In addition, room-temperature NInL deposition of conductor/dielectric materials enables the fabrication of small versatile devices and circuits. For demonstration, we fabricated a functional 16-nm six-transistor static random access memory (SRAM) cell (area: occupying only 0.039 mu m(2)), 43% the size of the smallest previously reported SRAM cell, using the FinFET structure and a dynamic V(dd) regulator approach. The NInL technique offers a new way of exploring low-volume high-value 16-nm complementary metal-oxide-semiconductor (CMOS) devices and circuit designs with minimal additional investment and obtains early access to extreme CMOS scaling.
A Numerical Study of Si-TMD Contact with n/p Type Operation and Interface Barrier Reduction for Sub-5 nm Monolayer MoS2 FET
(2016-01-01)
Tang, Ying-Tsan
;
Li, Kai-Shin
;
Li, Lain-Jong
;
Li, Ming-Yang
;
Lin, Chang-Hsien
An atomic-scale numerical study of Si contact with transition metal dichalcogenides (TMD) semiconductor materials is proposed by first-principles simulation for the first time. The monolayer MoS2 channel can be operated as both of n- and p-type FET by properly doping Si S/D to adjust the TMD channel potential. The gradient MoSx junction of dichalcogenide vacancies enables Si-MoS2 contact resistance lower than 100 Omega-mu m for interface Schottky barrier height reduction. The compact Si-MoS2 interface study can potentially provide monolayer TMD contact design guideline for the sub-5 nm TMD FET fabrication technology.
Bistable resistive switching in Al2O3 memory thin films
(2007)
Lin, Chih-Yang
;
Wu, Chen-Yu
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Wu, Chung-Yi
;
Hu, Chenming
;
Tsenga, Tseung-Yuen
In this study, we investigate the resistive switching behavior of radio frequency (rf)-sputtered Al2O3 thin films. It is observed that both high-conducting state (ON state) and low-conducting state (OFF state) are stable and reproducible during successive resistive switchings by dc voltage sweeping. The ratio of resistance of the ON and OFF state is over 10(3). Such a reproducible resistive switching can be performed at 150 degrees C, and the resistance of the ON state can be altered by various current compliances. The conduction mechanisms of the ON and OFF states are demonstrated as ohmic conduction and Frenkel-Poole emission, respectively. Both states, performed by dc voltage sweeping and applying short pulse, are stable over 10(4) s at a read voltage of 0.3 V and the electrical-pulse-induced resistance change (EPIR) phenomenon is demonstrated, which are all important properties for further resistive random access memory application. (c) 2007 The Electrochemical Society.
CIGS solar cell integrated with high mobility microcrystalline Si TFTs on 30X40 cm(2) glass panels for self powered electronics
(2012-01-01)
Shen, Chang-Hong
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Shieh, Jia-Min
;
Wu, Tsung-Ta
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Huang, Jung Y.
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Huang, Che-Hsuan
For the first time, we report a novel self-powered TFT panel (30X40cm(2)) by integration of sputtering/non-toxic Se vapor selenization copper-indium-gallium-selenide (CIGS) solar cell (conversion efficiency of 8%) and high electron-mobility (172 cm(2)/V-s) micro-crystalline (mu c)-Si TFTs.
Corner Spacer Design for Performance Optimization of Multi-Gate InGaAs-OI FinFET with Gate-to-Source/Drain Underlap
(2016)
Hu, Vita Pi-Ho
;
Lo, Chang-Ting
;
Sachid, Angada B.
;
Su, Pin
;
Hu, Chenming
Corner spacer design is investigated to improve the performance of multi-gate InGaAs-OI FinFET with gate-to-source/drain underlap compared with the all vacuum and all nitride spacer devices. All vacuum spacer devices with low permittivity reduce fringing capacitance and improve performance. However, for gate-to-source/drain underlap InGaAs-OI FinFET, all vacuum spacer device degrades source/drain resistance (Rsd) and ON current (Ion), thus exhibiting slight improvement in inverter delay compared with the all nitride spacer device. Corner spacer design comprising of high-k and low-k composite spacer is proposed to optimize Rsd and capacitance, and hence improve delay. Various lengths and heights of corner spacer for InGaAs-OI FinFET with different underlap length and fin height aspect ratio are investigated to optimized performance. The optimized corner spacer design is: (a) the length of corner spacer (Lcorner) is approximately equal to underlap length (Lun), and (b) the height of corner spacer (Hcorner) is proportional to the sum of fin height (Hfin) and gate oxide thickness (Tox). Compared with the all vacuum spacer InGaAs-OI FinFET with Lun = 6 nm, the optimized corner spacer design exhibits 36% and 10% improvements in Ion and inverter delay, respectively.
Effect of top electrode material on resistive switching properties of ZrO2 film memory devices
(2007-05-01)
Lin, Chih-Yang
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Wu, Chen-Yu
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Wu, Chung-Yi
;
Lee, Tzyh-Cheang
;
Yang, Fu-Liang
The influence of top electrode material on the resistive switching properties of ZrO2 -based memory film using Pt as a bottom electrode was investigated in this letter. In comparison with Pt/ZrO2/Pt and Al/ZrO2/Pt devices, the Ti/ZrO2/Pt device exhibits different resistive switching current-voltage (I-V) curve, which can be traced and reproduced by a dc voltage more than 1000 times only showing a little decrease of resistance ratio between high and low resistance states. Furthermore, the broad dispersions of resistive switching characteristics in the Pt/ZrO2/Pt and Al/ZrO2/Pt devices are generally observed during successive resistive switching, but those dispersions are suppressed by the device using Ti as a top electrode. The reliability results, such as cycling endurance and continuous readout test, are also presented. The write-read-erase-read operations can be over 104 cycles without degradation. No data loss is found upon successive readout after performing various endurance cycles.
Effects of Annealing on Ferroelectric Hafnium-Zirconium-Oxide-Based Transistor Technology
(2019-03-01)
Chen, Yi-Hsuan
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Su, Chun-Jung
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Hu, Chenming
;
Wu, Tian-Li
;
國際半導體學院
In this letter, we investigate annealing effects in ferroelectric HfZrOx dielectric in metal-insulator-metal devices and metal-oxide-semiconductor capacitors by comparing two annealing methods: rapid thermal annealing (RTA) and microwave annealing (MWA). The tradeoff characteristics between the annealing conditions, polarization-electric field characteristics, gate leakage current, and interface state density (D-it) are discussed. We show that: 1) a positive correlation between the remanent polarization (Pr), the gate leakage current, and D-it as the annealing temperature (RTA) and the annealing power (MWA) increase and 2) the MWA is promising for ferroelectric transistors technology, since its low thermal budget can minimize D-it and avoid increase in the gate leakage current.
Effects of the Variation of Ferroelectric Properties on Negative Capacitance FET Characteristics
(2016-05)
Lin, Cheng-I
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Khan, Asif Islam
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Salahuddin, Sayeef
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Hu, Chenming
;
電子工程學系及電子研究所
We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation (similar to +/- 3%) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (<= 5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized.
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits
(2019-04-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This paper examines metal-ferroelectric-insulator-semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse V-ds-dependence of threshold voltage (V-T), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low V-DD.
Evaluation of NC-FinFET Based Subsystem-Level Logic Circuits Using SPICE Simulation
(2018-01-01)
You, Wei-Xiang
;
Su, Pin
;
Hu, Chenming
;
電子工程學系及電子研究所
;
國際半導體學院
This work examines the metal-ferroelectricinsulator-semiconductor (MFIS) negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. With the aid of a short-channel NC-FinFET compact model, we confirm the functionality and determine the standby-power/switching-energy/delay performance of logic circuits (5-stage inverter and 4-bit Manchester carry-chain (MCC) adder) employing 14nm ULP NC-FinFETs versus FinFETs. We show that the inverse V-ds-dependency of threshold voltage (V-T), also known as the negative DIBL, of NCFET is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTI.) circuits, especially for the PTI, at low V-DD.
Fast programming metal-gate Si quantum dot nonvolatile memory using green nanosecond laser spike annealing
(2012-04-02)
Lien, Yu-Chung
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Shieh, Jia-Min
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Huang, Wen-Hsien
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Tu, Cheng-Hui
;
Wang, Chieh
The ultrafast metal-gate silicon quantum-dot (Si-QD) nonvolatile memory (NVM) with program/erase speed of 1 mu s under low operating voltages of +/-7V is achieved by thin tunneling oxide, in situ Si-QD-embedded dielectrics, and metal gate. Selective source/drain activation by green nanosecond laser spike annealing, due to metal-gate as light-blocking layer, responds to low thermal damage on gate structures and, therefore, suppresses re-crystallization/deformation/diffusion of embedded Si-QDs. Accordingly, it greatly sustains efficient charge trapping/de-trapping in numerous deep charge-trapping sites in discrete Si-QDs. Such a gate nanostructure also ensures excellent endurance and retention in the microsecond-operation Si-QD NVM. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.3700729]
Full Low Temperature Microwave Processed Ge CMOS Achieving Diffusion-Less Junction and Ultrathin 7.5nm Ni Mono-Germanide
(2012-01-01)
Lee, Y. -J.
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Chuang, S. -S.
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Liu, C. -I.
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Hsueh, F. -K.
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Sung, P. -J.
For the first time, Ge CMOS with all thermal processes performed by microwave annealing (MWA) has been realized. The full MWA process is under 390 degrees C. It significantly outperforms conventional rapid thermal annealing (RTA) process in 3 aspects: (1) Diffusion-less junction: for easily diffused n-type dopant, phosphorous (P), the ion implantation dopant profile after the MWA activation process remains unchanged. (2) Increased C-ox and lower gate leakage: the low temperature activation process leads to less Ge out-diffusion during MWA than RTA, suppressing the degradation of gate dielectric/ Ge channel interface. (3) Ultrathin 7.5nm Ni mono-germanide with low sheet resistance (Rs) and contact resistivity: after two-step MWA, a thin mono-NiGe layer was obtained which has larger crystallite size to lower Rs. Ge n- and p-MOSFET were also demonstrated. Compared to conventional RTA, the MWA gives 50% and 24% drive current enhancement for p- and n-MOSFET, respectively. These data show that the low temperature MWA is a very promising thermal process technology for Ge CMOS manufacturing.
Hybrid Si/TMD 2D Electronic Double Channels Fabricated Using Solid CVD Few-Layer-MoS2 Stacking for V-th Matching and CMOS-Compatible 3DFETs
(2014)
Chen, Min-Cheng
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Lin, Chia-Yi
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Li, Kai-Hsin
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Li, Lain-Jong
;
Chen, Chang-Hsiao
Stackable 3DFETs such as FinFET using hybrid Si/MoS 2 channels were developed using a fully CMOS-compatible process. Adding several molecular layers (3-16 layers) of the transition-metal dichalcogenide (TMD), MoS2 to Si fin and nanowire resulted in improved (+25%) I-on,I-n of the FinFET and nanowire FET (NWFET). The PFETs also operated effectively and the N/P device V-th are low and matched perfectly. The proposed heterogeneous Si/TMD 3DFETs can be useful in future electronics.
Improved TDDB Reliability and Interface States in 5-nm Hf0.5Zr0.5O2 Ferroelectric Technologies Using NH3 Plasma and Microwave Annealing
(2020-04-01)
Chen, Yi-Hsuan
;
Su, Chun-Jung
;
Yang, Ting-Hsin
;
Hu, Chenming
;
Wu, Tian-Li
This article reports that the enhanced forward gate bias time-dependent dielectric breakdown (TDDB) reliability and interface quality are achieved in 5-nm ferroelectric Hf0.5Zr0.5O2 (HZO) technologies by using the NH3 plasma interfacial layer (IL) treatment and microwave annealing (MWA). An orthorhombic crystalline phase is observed in the annealed HZO film with NH3 plasma IL treatment and MWA, and NH3 plasma IL treatment can suppress Hf/Zr interdiffusion. Metal-oxide-semiconductor capacitors (MOSCAPs) subjected to NH3 plasma IL treatment and 2100-W MWA also have a higher extrapolated operating voltage for a ten-year lifetime at 0.01% failure and lower interface state density compared to the devices subjected to only rapid thermal annealing (RTA) at 600 degrees C. Therefore, NH3 plasma treatment and MWA are effective for improving the TDDB reliability and interface quality of the ultrathin ferroelectric HZO.
In0.53Ga0.47As FinFET and GAA-FET With Remote-Plasma Treatment
(2018-03-01)
Luc, Quang Ho
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Yang, Kun Sheng
;
Lin, Jia Wei
;
Chang, Chia Chi
;
Huy Binh Do
This letter presents a remote NH3/N-2 plasma treatment after gate oxide deposition for improving the electrical characteristics and the reliability of In0.53Ga0.47As FinFET. The plasma treatment enhanced drive current (I-DS), transconductance (G(m)), subthreshold swing (SS), flicker noise, and positive bias temperature lifetime, suggesting that this plasma treatment significantly improves the quality of the etched In0.53Ga0.47As channel interface. In0.53Ga0.47As FinFETs and gate-all-around FETs were fabricated with the proposed in situ remote-plasma treatment and characterized.
Investigation of Mo/Ti/AlN/HfO2 High-k Metal Gate Stack for Low Power Consumption InGaAs NMOS Device Application
(2017-05-01)
Huy Binh Do
;
Quang Ho Luc
;
Minh Thien Huu Ha
;
Sa Hoang Huynh
;
Tuan Anh Nguyen
Use of the Mo/Ti/AlN/HfO2 metal/dielectric stack to increase the permittivity of HfO2 for low power consumption InGaAs-based MOSFET is investigated in this letter. The dielectric constant of HfO2 was found to increase by 47%, from 17 to 25, after Ti doping without affecting the interface trap density around the mid-gap of the MOSCAPs. A strong inversion behavior with low leakage current for the MOSCAP was also observed. The gate voltage needed to tune the Fermi level of InGaAs channel was found to be smaller for the Ti-doped HfO2 sample as compared with the sample with un-doped HfO2. The increase of the dielectric constant of HfO2 after Ti doping combined with the use of Ti gate metal, which has the work function level near the conduction band edge of InGaAs, makes the proposed Mo/Ti/HfO2 (Ti) stackideal for future lowpower consumption InGaAs-based NMOS applications.
Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits
(2018-01-01)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Po-Tsang
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Chen, Kuan-Neng
;
Wu, Wan-Chi
A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO2. The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/doc.), high driving currents (n-type: 363 mu A/mu m and p-type: 385 mu A/mu m), and high I-on/I-off(>10(6)). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 degrees C.