Browsing by Author "Hu, Yu-Chen"

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3D Heterogeneous Integration Structure Based on 40 nm- and 0.18 mu m- Technology Nodes
(2015)
Hu, Yu-Chen
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Lin, Chun-Pin
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Hsieh, Yu-Sheng
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Chang, Nien-Shyang
;
Gallegos, Anthony J.
In this paper, a simple process for high yield CMOS-compatible and heterogeneous integrated chip-to-chip structure without TSV is demonstrated. This scheme provides two chips consisted of the shortest interconnect path by Cu/Sn pillar bump and electroless nickel immersion gold (ENIG) pad bonding. One of the key technologies of 3D integration process is bump plating on the uneven topography. Since passivation layer covers the periphery of the top metal layer, subsequent electroplating process resulted to the increase in height of bump edge which is higher than bump center resulting in concave shape. A new and unique plating solution was developed to solve the issue during the electroplating pillar bump. Basic electrical characteristics including resistance and current leakage were investigated with reliability tests. The stable reliability tests results and excellent electrical performance show that the 3D heterogeneous integration structure is potentially applicable for 3D applications in the future.
A 64-CHANNEL WIRELESS NEURAL SENSING MICROSYSTEM WITH TSV-EMBEDDED MICRO-PROBE ARRAY FOR NEURAL SIGNAL ACQUISITION
(2017-01-01)
Huang, Yu-Chieh
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Huang, Po-Tsang
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Hu, Yu-Chen
;
Wu, Shang-Lin
;
You, Yan-Huei
To enhance the signal integrity of high-density neural-sensing signals, this work presents an implantable high spatial resolution mu-probe array with through-silicon via (TSV) 2.5D integration technology that realizes a miniaturized implantable device on flexible printed circuit (FPC) interposer. The proposed microsystem was composed of two 32-channel neural sensing chips and one radio frequency chip for neural signal processing. The mu-probe array can achieve better signal-to-noise ratio with neural-signal acquisition and processing circuit composed of a pseudo-resistor-based analog front-end amplifier. Moreover, a receiving antenna is also implemented on the backside of FPC for wireless data and power transmission. The feasibility of the proposed mu-probe array, Tx and Rx antenna, 32-channel neural sensing circuits in the 64-channel wireless microsystem have been successfully demonstrated for future integration and animal experiments.
A Novel Bonding Approach and Its Electrical Performance for Flexible Substrate Integration
(2016-07-01)
Hu, Yu-Chen
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Chen, Kuan-Neng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A novel bonding approach for flexible substrate vertical stacking is proposed in this paper. Unlike the traditional anisotropic conductive/non-conductive paste/film used in flexible substrate bonding, the metal thin film is adopted as bonding material in this approach. Experiment results show that the novel bonding approach has good electrical properties and reliability performances. The innovative bonding approach is considered a breakthrough of the traditional restrictions in flexible substrates, including I/O pitch, electrical reliability, and bonding conditions. This development is expected to contribute to the fabrication of future flexible substrate stacking.
A Novel Flexible 3-D Heterogeneous Integration Scheme Using Electroless Plating on Chips With Advanced Technology Node
(2015-12-01)
Hu, Yu-Chen
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Lin, Chun-Pin
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Chang, Yao-Jen
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Chang, Nien-Shyang
;
Sheu, Ming-Hwa
A novel 3-D chip-level heterogeneous integration scheme for low cost and rapid pilot demonstration is proposed in this paper. The conventional Bumping fabrication is done at wafer level. However, due to the high cost of whole wafer, opting for chips with advanced technology node is a better alternative. Therefore, with the difficulties of the bumping process at chip level, 3-D heterogeneous integration by chip stacking faces challenges. This paper presents a novel heterogeneous integration platform by using electroless plating on chips and pillar bump on wafers before stacking. This integration platform can be applied to chip-to-chip or chip-to-wafer scheme when chips are fabricated from costly advanced technology node.
Advanced Crystal Component Package with Silicon TSV Interposer Using 3D Integration and Novel SU-8 Polymer Sealing Bonding Structure
(2014)
Shih, Jian-Yu
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Chen, Yen-Chi
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Lee, Shih-Wei
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Hu, Yu-Chen
;
Chiu, Chih-Hung
In this paper, a novel crystal component package based on silicon TSV interposer substrate is demonstrated by using 3D integration technologies. It is distinct from conventional crystal component using ceramic-based substrate. This crystal component with advanced silicon-based substrate shows great manufacturability to replace traditional fabrication approach. In addition, the SU-8 sealing bonding structure provides the possibility to substitute for the conventional metal lid with reliability investigation. Finally, a novel silicon-based crystal component package with 3D integration is successfully fabricated through general semiconductor techniques to replace traditional manufacture.
Advanced TSV-Based Crystal Resonator Devices Using 3-D Integration Scheme With Hermetic Sealing
(2013-08-01)
Shih, Jian-Yu
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Chen, Yen-Chi
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Chiu, Chih-Hung
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Hu, Yu-Chen
;
Lo, Chung-Lun
An advanced crystal resonator device scheme using Cu through-silicon via (TSV), 3-D integration, and Si packaging technologies is successfully demonstrated. In addition to robust structural quality, the crystal resonator packaging has excellent electrical characteristics of low leakage current and reliability against harsh environment for MIL-STD-883 hermetic encapsulation. Using 3-D integration technologies and Si packaging, the proposed TSV-based crystal resonator device possesses the manufacturability potential while conventional ones using a metal lid or ceramic enclosure.
An Advanced 2.5-D Heterogeneous Integration Packaging for High-Density Neural Sensing Microsystem
(2017-04-01)
Hu, Yu-Chen
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Huang, Yu-Chieh
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Huang, Po-Tsang
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Wu, Shang-Lin
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Chang, Hsiao-Chun
In the traditional neural sensing microstructure, the limited metal line pitch and the metal layer numbers restrict the neural signal routing ability from electrodes to circuit chips. Miniature packaging and excessive noise interference bottlenecks are some of the challenges faced by the electrodes and circuit chips integration with traditional wire bonding. This paper proposes a 2.5-D heterogeneous integration neural sensing microsystem based on the silicon substrate to overcome these issues. With standard semiconductor and 3-D integration processes, high-channel-density (256 channels at 25 mm(2)) neural sensing microsystem is achieved. Through silicon via provides the shortest vertical interconnection and dramatically minimizes the packaging. Furthermore, the interposer can carry multiple chips to enhance the function of the biosensor. Electrical characteristics and reliability examinations reveal its high quality and great performance as compared to traditional approaches. This novel highly integrated neural sensing microsystem is expected to contribute to the biomedical field for exploring and solving unknown biological mysteries.
An Advanced 3D/2.5D Integration Packaging Approach Using Double-Self-Assembly Method with Complex Topography, and Micropin-Fin Heat Sink Interposer for Pressure Sensing System
(2016-01-01)
Hu, Yu-Chen
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Lin, Chun-Pin
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Chang, Hsiao-Chun
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Yang, Yu-Tao
;
Chen, Chi-Shi
To cater complex topography sensors and circuit chips for smart lifestyle applications using Internet of Things (IoT), we develop a novel efficient double-self-assembly packaging approach by 3D/2.5D heterogeneous integration. This technology is able to integrate various kinds of processed chips, especially with uneven surface and bottom topography. With liquid surface tension, complex topography chips can be handled and self-aligned on precise locations. Double-self-assembly approach demonstrates temporary bonding on carrier wafer and self-aligned permanent bonding in a pressure sensing system packaging. The optimized volume of liquid to use on various complex topography shapes and areas are investigated, while Cu/In low temperature metal bonding and self-assembly approach for high I/O density and low bonding resistance are demonstrated. Excellent electrical characteristics and mechanical strength of show the feasibility of the double-self-assembly approach on complex topography surface chips packaging applications.
An Implantable 128-Channel Wireless Neural-Sensing Microsystem using TSV-Embedded Dissolvable mu-Needle Array and Flexible Interposer
(2017-01-01)
Huang, Po-Tsang
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Huang, Yu-Chieh
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Wu, Shang-Lin
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Hu, Yu-Chen
;
Lu, Ming-Wei
For implanted neural-sensing devices, one of the remaining challenges is to transmit stable power/data (P/D) transmission for high spatiotemporal resolution neural data. This paper presents a miniaturized implantable 128-channel wireless neural-sensing microsystem using TSV-embedded dissolvable mu-needle array, a flexible interposer and 4 dies by 2.5D/3D TSV heterogeneous SiP technology. The 4 dies are 2 neural-signal acquisition ICs implemented by 90nm CMOS, 1 neural-signal processor by 40nm CMOS and 1 wireless P/D transmission circuitry by 0.18 mu m CMOS. Thus, the proposed wireless microsystem realizes 128-channel neural-signal sensing within the area of 5mm x 5mm, neural feature extraction and wireless P/D transmission using an on-interposer inductor. The overall average power of the circuits in this microsystem is only 9.85mW.
Development and Electrical Performance of Low Temperature Cu-Sn/In Bonding for 3D Flexible Substate Integration
(2016)
Hu, Yu-Chen
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Chen, Kuan-Neng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An innovative bonding approach applied to flexible substrate bonding is proposed in this research. Thin-film metal pad is fabricated as bonding medium to provide vertical stacking. As compared to other bonding methods, such as anisotropic conductive film (ACF) or non-conductive paste (NCP), thin-film metal pad bonding approach provides the most attractive advantage of fine-pitch. The bonding condition at low temperature exhibits good electrical performance, proving its great potential in the applications of flexible substrate stacking.
Graphene oxide sensitizes cancer cells to chemotherapeutics by inducing early autophagy events, promoting nuclear trafficking and necrosis
(2018-01-01)
Lin, Kuan-Chen
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Lin, Mei-Wei
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Hsu, Mu-Nung
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Guan Yu-Chen
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Chao, Yu-Chan
Rationale: Cisplatin (CDDP) is a broad-spectrum anticancer drug but chemoresistance to CDDP impedes its wide use for cancer therapy. Autophagy is an event occurring in the cytoplasm and cytoplasmic LC3 puncta formation is a hallmark of autophagy. Graphene oxide (GO) is a nanomaterial that provokes autophagy in CT26 colon cancer cells and confers antitumor effects. Here we aimed to evaluate whether combined use of GO with CDDP (GO/CDDP) overcomes chemoresistance in different cancer cells and uncover the underlying mechanism. Methods: We treated different cancer cells with GO/CDDP and evaluated the cytotoxicity, death mechanism, autophagy induction and nuclear entry of CDDP. We further knocked down genes essential for autophagic flux and deciphered which step is critical to nuclear import and cell death. Finally, we performed immunoprecipitation, mass spectrometry and immunofluorescence labeling to evaluate the association of LC3 and CDDP. Results: We uncovered that combination of GO and CDDP (GO/CDDP) promoted the killing of not only CT26 cells, but also ovarian, cervical and prostate cancer cells. In the highly chemosensitized Skov-3 cells, GO/CDDP significantly enhanced concurrent nuclear import of CDDP and autophagy marker LC3 and elevated cell necrosis, which required autophagy initiation and progression but did not necessitate late autophagy events (e.g., autophagosome completion and autolysosome formation). The GO/CDDP-elicited nuclear trafficking and cell death also required importin alpha/beta, and LC3 also co-migrated with CDDP and histone H1/H4 into the nucleus. In particular, GO/CDDP triggered histone H4 acetylation in the nucleus, which could decondense the chromosome and enable CDDP to more effectively access chromosomal DNA to trigger cell death. Conclusion: These findings shed light on the mechanisms of GO/CDDP-induced chemosensitization and implicate the potential applications of GO/CDDP to treat multiple cancers.
Integration of Neural Sensing Microsystem with TSV-embedded Dissolvable mu-Needles Array, Biocompatible Flexible Interposer, and Neural Recording Circuits
(2016)
Huang, Yu-Chieh
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Hu, Yu-Chen
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Huang, Po-Tsang
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Wu, Shang-Lin
;
You, Yan-Huei
Local brain connectivity is expected to lead to new models for neurological diseases, which may in turn result in advanced understanding and better treatment. This paper presents a neural sensing microsystem integrated with TSV-embedded dissolvable mu-needles array, ENIG bonding technology, biocompatible Au-TSV flexible interposer and neural recording circuits, for neural sensing implantation. An ultra-thin film bonding approach is proposed for integration of interposer assembly. Removing bonding wire by proposed bonding technology, the dimension of neural sensing system can be minimized to reduce surgical area and promote implant success rate. The signal quality of neural recording can be significantly improved by eliminating complex signal paths with 2.5D TSV integration from neural sensing interface to neural recording circuits.
Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration
(2012)
Chiang, Cheng-Hao
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Hu, Yu-Chen
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Chen, Kuo-Hua
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Chiu, Chi-Tsung
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Chuang, Ching-Te
Bosch reactive ion etching is widely used for TSV formation. The micro-masking formed during etching can be successfully removed by adjusting the internal parameters during etching. The smooth high-aspect-ratio TSVs were further developed in wafer-level fabrication. Finally, a two-step etching process was developed to achieve tapered TSVs for the following Cu plating process.
Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations
(2012)
Hu, Yu-Chen
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Chiang, Cheng-Hao
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Chen, Kuo-Hua
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Chiu, Chi-Tsung
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Chuang, Ching-Te
In this paper, a detailed examination on TSV and cavity inductive coupled plasma (ICP) etching is presented. We investigated the relation such as etching loop number, TSV etching depth and etching rate. Due to particles knocked off from the hard mask and then fallen down to the TSV and cavity bottom, micro-masking issue becomes serious after ICP etching. In addition, parameters of isotropic etching, pressure, and RF bias were studied to investigate the process of micro-masking removal.
Reliability Investigation and Mechanism Analysis for a Novel Bonding Method of Flexible Substrate in 3D Integration
(2016-01-01)
Yang, Yu-Tao
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Hu, Yu-Chen
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Chen, Kuan-Neng
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A breakthrough in vertical stacking and bonding method in flexible substrates is developed and presented in this paper. Unlike current ACF and NCP approaches, which are used in most manufacturing industry, our novel stacking method uses only metal thin film as bonding material. Two different bonding material bumps are carried out in our experiment. Both show better electrical and reliability outcomes compared to current methods. Our proposed method can reach ultra-fine pitch, metal bonding without polymer material, simplified manufacturing process, better electrical performance and less reliability issues. It can be considered as a future bendable and flexible substrate stacking approach.
Research of Electroplating and Electroless Plating for Low Temperature Bonding in 3D Heterogeneous Integration
(2014)
Hu, Yu-Chen
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Chang, Yao-Jen
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Wu, Chun-Shen
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Cheng, Yung Mao
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Chen, Wei Jen
In this paper, a 3D chip-to-chip hetero-integration scheme without Si interposer is demonstrated under 270 degrees C thermal budget. The scheme successfully integrates advanced and common technology node logic chips by Cu/Sn to ENIG bumping. Cu/Sn mu-bumps are electroplated on common technology node and ENIG joints are electroless-plated on advanced technology node opening pads, respectively. Herein, 60 mu m bump pitch, 40 mu m diameter of Cu/Sn mu-bump and 50 mu m diameter of ENIG are presented. Without cracks and voids, the 3D C2C scheme gives an efficient approach for future development of 3D IC.
Sealing Bump With Bottom-Up Cu TSV Plating Fabrication in 3-D Integration Scheme
(2013-05-01)
Chiang, Cheng-Hao
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Kuo, Li-Min
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Hu, Yu-Chen
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Huang, Wen-Chun
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Ko, Cheng-Ta
A sealing bump approach for the simplification of the conventional bottom-up copper through-silicon via (TSV) plating process flow is developed to reduce the process steps and increase the throughput without sacrificing the structure integrity and electrical performance. In this approach, TSV and bump formation can be achieved simultaneously through the bottom-up plating. Results from the analysis reveal excellent electrical characteristics and quality examination, which indicate that the proposed approach may be a good candidate for the TSV fabrication in 3-D integration.
TSV-Based Quartz Crystal Resonator Using 3D Integration and Si Packaging Technologies
(2013)
Shih, Jian-Yu
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Chen, Yen-Chi
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Chiang, Cheng-Hao
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Chiu, Chih-Hung
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Hu, Yu-Chen
In this paper, one novel packaging approach for crystal resonator with the quartz crystal is demonstrated, developed and characterized. The proposed crystal resonator of the novel package adopts several 3-D core technologies, such as Cu TSVs, thin-film Cu/Sn eutectic bonding, and wafer thinning. A 1210 crystal resonator with quartz blank mount is successfully developed with Cu TSVs that enables the electrical connection of the signal electrode on the quartz blank. The quartz blank is protected by the simultaneous formation of strength reinforcement and excellent sealing capacity of thin-film Cu/Sn eutectic bonding. With the well fabrication and the enhanced structure, excellent leakage results in the MIL-STD-883 hermetic test (8.5*10(-9) similar to 1*10(-8) Pa m(3)/sec by He leak detector) show the crystal resonator using 3D integration has the great performance and manufacturability to replace the conventional metal or ceramic enclosures for the next generation products.
Ultrahigh-Density 256-Channel Neural Sensing Microsystem Using TSV-Embedded Neural Probes
(2017-10-01)
Huang, Yu-Chieh
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Huang, Po-Tsang
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Wu, Shang-Lin
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Hu, Yu-Chen
;
You, Yan-Huei
Highly integrated neural sensing microsystems are crucial to capture accurate signals for brain function investigations. In this paper, a 256-channel neural sensing microsystem with a sensing area of 5 x 5 mm(2) is presented based on 2.5-D through-silicon-via (TSV) integration. This microsystem composes of dissolvable mu-needles, TSV-embedded mu-probes, 256-channel neural amplifiers, 11-bit area-power-efficient successive approximation register analog-to-digital converters, and serializers. This microsystem can detect 256 electrocorticography and local field potential signals within a small area of 5 mm x 5 mm. The neural amplifier realizes 57.8 dB gain with only 9.8 mu W per channel. The overall power of this microsystem is only 3.79mW for 256-channel neural sensing. A smaller microsystem with dimension of 6 mm x 4 mm has been also implanted into rat brain for somatosensory evoked potentials (SSEPs) recording by using contralateral and ipsilateral electrical stimuli with intensity from 0.2 to 1.0 mA, and successfully observed different SSEPs from left somatosensory cortex of a rat.
Uneven-Topography-Chip Packing Approach Using Double-Self-Assembly Technology for 3-D Heterogeneous Integration
(2018-02-01)
Shen, Wen-Wei
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Chang, Hsiao-Chun
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Yang, Yu-Tao
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Hu, Yu-Chen
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Chen, Kuan-Neng
Although chip-level heterogeneous integration has high yield for production, low-throughput issue of chip-to-wafer bonding is necessary to be improved. Due to the uneven topography and small chip size, handling issue and alignment accuracy are important factors that impact the difficulty in heterogeneous integration. Self-assembly technology has a high potential to be applied in 3-D heterogeneous integration. By using hydrophobic film to define the stacking area, hydrophilic chips can be assembled to realize alignment process on these areas through wafer surface tension in a very short time. With this concept, double-self-assembly technology is accomplished to resolve both handling and alignment issues for uneven-topography-chip integration. In this paper, different chip sizes of mu-pillar are simulated to investigate the optimal water volume for double-self-assembly process. High alignment accuracy of misalignment measurement can be accomplished with the optimal water volume. Furthermore, microstructure of Cu/In bonded structures and corresponding electrical analyses are evaluated, while various reliability tests are investigated for bonding quality. Excellent results verify that the double-self-assembly technology could be applied to 3-D heterogeneous integration for uneven-topography-chip integration.