Browsing by Author "Hu, Yu-Hao"

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40 nm Bit-Interleaving 12T Subthreshold SRAM With Data-Aware Write-Assist
(2014-09-01)
Chiu, Yi-Wei
;
Hu, Yu-Hao
;
Tu, Ming-Hsien
;
Zhao, Jun-Kai
;
Chu, Yuan-Hua
This paper presents a new bit-interleaving 12T sub-threshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to improve the Write-ability to mitigate increased device variations at low supply voltage under deep sub-100 nm processes. The disturb-free feature facilitates the bit-interleaving architecture that can reduce multiple-bit errors in a single word and enhance soft error immunity by employing error checking and correction (ECC) techniques. The proposed 12T SRAM cell is demonstrated by a 4 kb SRAM macro implemented in 40 nm general purpose (40GP) CMOS technology. The test chip operates from typical V-DD to 350 mV (similar to 100 mV lower than the threshold voltage) with V-DDMIN limited by Read operation. Data can be written successfully for V-DD down to 300 mV. The measured maximum operation frequency is 11.5 MHz with total power consumption of 22 mu W at 350 mV, 25 degrees C.
A 40 nm 0.32 V 3.5 MHz 11T Single-Ended Bit-Interleaving Subthreshold SRAM with Data-Aware Write-Assist
(2013)
Chiu, Yi-Wei
;
Hu, Yu-Hao
;
Tu, Ming-Hsien
;
Zhao, Jun-Kai
;
Jou, Shyh-Jye
This paper presents a new bit-interleaving 11T subthreshold SRAM cell with Data-Aware Power-Cutoff (DAPC) Write-assist to mitigate the leakage and variation and improve the Write-ability in deep sub-100nm technology. Measurement results from a 4 Kb test chip implemented in 40 nm General Purpose (40GP) CMOS technology operates for V-DD down to 0.32 V (similar to 0.69X of threshold voltage) with V-DDMIN limited by Read operation. The measured maximum operation frequency is 3.5 MHz (16.5 MHz) at 0.32 V (0.38 V) with total power consumption of 15.2 mu W (27.2 mu W) at 25 degrees C.
A Subthreshold SRAM with Embedded Data-Aware Write-Assist and Adaptive Data-Aware Keeper
(2016)
Chiu, Yi-Wei
;
Hu, Yu-Hao
;
Zhao, Jun-Kai
;
Jou, Shyh-Jye
;
Chuang, Ching-Te
We propose a data-aware power cut-off write-assist 12T SRAM cell (DPC12T) which improves the write-ability to improve the write minimum operating voltage (V-MIN). Moreover, we propose an adaptive data-aware keeper (DAK) to lower the design conflicts among the keeper current, read current and the bit-line leakage current to improve the read stability and read V-MIN for single-ended read operation. Fabricated 40nm 8kb test chip macro with 64 cells per bit-line can achieve V-MIN 250 mV and 230 mV without and with enabling DAK at 6 MHz and 4 MHz, respectively. The SRAM test macro with 256, 512 and 1024 cells per bit-line demonstrates that DAK improves the read V-MIN by 9% to 21% at low supply voltages.