Browsing by Author "Huang, Shih-Che"

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A statistical model for simulating the effect of UPS TFT device variation for SOP applications
(2007-12-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
;
Chen, Wan-Ping
;
Chao, Yu-Te
;
Chou, Yen-Pang
In this paper, the variation characteristics of low-temperature polycrystalline silicon (LTPS) thin-film transistors (TFTs) are investigated with a statistical approach. A special layout is proposed to investigate the device variation with respect to various devices distances. Two non-Gaussian equations are proposed to fit the device parameter distributions, whose the coefficients of determination (R(2)) are both near 0.9, reflecting the validity of the model. Two benchmark circuits are used to compare the difference between the proposed model and the conventional Gaussian distribution for the device parameter distribution. The output behaviors of the digital and analog circuits show that the variation in the short range would greatly affect the performance of the analog circuits and would instead be averaged in the digital circuits.
Analysis of P-type poly-Si TFT degradation under dynamic gate voltage stress using the slicing model
(2007)
Huang, Shih-Che
;
Tsao, Hung-Chuan
;
Tai, Ya-Hsiang
;
光電工程學系
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Department of Photonics
In this work, the mobility degradation after gate AC stress in the off region are examined. It is discovered that the mobility increases after AC gate stress condition 0 V to + 15 V, which the previously reported model (by Uraoka. Y) may not explain. Considering the spatial distribution of the voltage and the flow of the carriers in the channel, we proposed the slicing model", that is, replace the original TFT by ten TFTs with shorter channel length. Then, by applying the circuit simulator, the voltage distribution in the channel under different stages of gate applied voltage may be obtained. An index considering the current flow and the channel voltage at the edge nodes are proposed to describe the degradation in mobility. The fair linearity between the proposed index and the degradation in mobility reveals the validity of the proposed model.
Analysis of poly-Si TFT degradation under gate pulse stress using the slicing model
(2006-12-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
;
Chen, Chien-Kwen
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光電工程學系
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顯示科技研究所
The device degradation of polycrystalline-silicon thin-film transistors stressed with different gate pulse waveforms is investigated. It is first observed that the degradation is dependent on the rising time of the gate pulses for the gate voltage swing below the threshold voltage. The degradation ratio of the mobility is analyzed with respect to two factors, namely, the magnitude of the lateral transient electric field and the change in the numbers of the carrier near the edges of the channel. A new index considering these two factors is proposed to depict the device degradation. It shows good linearity between the degradation in mobility and the proposed index.
Capacitance-voltage behaviors of the LTPS TFTs before and after DC stress explained by the slicing model
(2007)
Kuo, Yan-Fu
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Huang, Shih-Che
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Chao, Yu-Te
;
Tai, Ya-Hsiang
;
光電工程學系
The proposed analytical circuit based on the slicing model further explains the behavior of the gate-to-source capacitance CGS and gate-to-drain capacitance CGD curves of the LTPS TFT at different measuring frequencies. The degradation mechanisms and damaged locations can be identified according to the frequency responses of the CGS and CGD curves.
Characterization of device degradation of poly-Si TFTs under dynamic operation with drain biased
(2008)
Tai, Ya-Hsiang
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Huang, Shih-Che
;
Chan, Chang-Lung
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光電工程學系
;
Department of Photonics
Poly-Si TFTs, which have the similar structures to the MOSFETs, are now having extensive studies for the applications in display system. The high device mobility of these devices enables the possibility to form both the in-pixel switches and integrated circuits with the poly-Si technology, which may greatly reduce the process complexity and fabrication cost. [1] Though recently several kinds of products formed with poly-Si technology had hit the market, the degradation mechanisms of the devices under dynamic operation with the drain biased are still not so clear. Y. Uraoka previously reported that the degradation behavior of the devices under gate AC operation with source/drain grounded is as a result of the swept carriers as the device is about to be turned off. [2] We have also reported that the degradation for the device operated in the off region as the source/drain grounded is because of the discharge behavior in the channel as the gate voltage toggling in the off region. [3] But these stress conditions are still far from the real operation conditions in applications. In this work, the degradation of the poly-Si TFTs under gate dynamic operation with drain biased, which would be much similar to the conditions operated in real applications, is carefully investigated.
Characterization of poly-Si TFT variation using interdigitated method
(2008-08-01)
Huang, Shih-Che
;
Tai, Ya-Hsiang
;
光電工程學系
;
顯示科技研究所
;
Department of Photonics
In this paper, the device variation characteristic of poly-Si TFTs is statistically investigated. First the variation of devices is examined with respect to different device distance. It is found that the device variation would exhibit similar behavior for different device distance. Then, in order to study the method to suppress device variation, the interdigitated layout is adopted. It is found that though the variation behavior of the poly-Si TFTs is much more serious and complicated than MOSFETs, the law of area can still be utilized to describe the variation behavior in the interdigitated layout. The fitting parameters in law of area can provide insights for understanding the intrinsic variation behavior for poly-Si TFTs and the discussion about the variation for the device with various channel width is provided. The variation behavior of poly-Si TFTs is then compared with amorphous silicon TFTs and single crystal silicon MOSFETs. The impacts of poly-Si TFT variation on circuit design and performance is also discussed. (C) 2008 Elsevier Ltd. All rights reserved.
Characterization of the Channel-Shortening Effect on P-Type Poly-Si TFTs
(2010-03-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Chen, Po-Ting
;
光電工程學系
;
顯示科技研究所
The phenomenon of channel shortening for p-type poly-Si thin-film transistors (TFTs) after stress is studied in this paper. Increased mobility, shifted threshold voltage V(TH), and reduced leakage current for the stressed device are observed. In addition, the capacitance-voltage (C-V) behavior for the stressed device exhibits the anomalous increase for the measuring gate voltage in the OFF region. A model illustrating how the trap electron mechanism would occur is provided. Furthermore, the degradation behavior of the p-type poly-Si TFT under gate ac stress in the OFF region is also studied. Similar degradation behaviors are observed for the gate-ac-stressed TFT for both of their I-V and C-V characteristics. A distributed device circuit model is proposed, and based on this model, it is proposed that the main voltage drop during gate ac stress in the OFF region could occur at the source and drain junction, which may, in turn, degrade the device. A gated p-i-n device under the same process condition is then adopted and dc stressed to verify the proposed mechanism. The similarity between the capacitance curves for the ac-stressed TFT and the dc-stressed gated p-i-n device proves the validity of the proposed mechanism.
Degradation Mechanism of Poly-Si TFTs Dynamically Operated in OFF Region
(2009-03-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Chen, Po-Ting
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光電工程學系
;
顯示科技研究所
This letter reports the study of the reliability behavior of poly-Si thin-film transistors (TFTs) with the pulsed gate voltage lower than the threshold voltage. First, the equivalent circuit model for poly-Si TFT is proposed. Considering the voltage drop for each element in the circuit model during the OFF-region gate dynamic stress, it is proposed that the main voltage drop occurs at the source and drain junctions, which could in turn degrade the device during stress. Based on this assumption, the gated p-i-n device fabricated on the same glass with the identical process conditions is stressed and analyzed. The similarity between the capacitance curves of the TFTs and gated p-i-n devices after stress proves that the main reason for degradation of poly-Si TFTs under gate OFF region ac stress is the large Voltage drop across the source and drain junctions.
Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress
(2007)
Tai, Ya-Hsiang
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Huang, Shih-Che
;
Lin, Chien Wen
;
Chiu, Hao Lin
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光電工程學系
In this paper, the degradation of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dc stress is investigated with measurement of the capacitance between the source and the gate (C-GS), as well as the capacitance between the drain and the gate (C-GD). It is discovered that the degradation in C-GD curves of the device after hot carrier stress shows apparent frequency dependence, while that in the C-GS curves remains almost the same. A circuit model based on the channel resistance extracted from the current-voltage behavior is proposed to describe the frequency dependence of the capacitance behavior. From this model, it is revealed that the anomalous frequency-dependent capacitance-voltage characteristics may simply reflect the transient behaviors of the channel resistances. Besides, it was found that the C-GS curves after self-heating effect exhibit a significant shift in the positive direction and an additional increase for the smaller gate voltage, while the C-GD curves show only positive shifts. By employing simulation, it was proved that the self-heating effect creates interface states near the source region and increases the deep states in the poly-Si film near drain. The proposed circuit model further explains the behavior of the C-GS and C-GD curves for the stressed device at different measuring frequencies. (C) 2007 The Electrochemical Society.
Dynamic stress effects on the reliability of poly-Si TFT
(2007)
Kuo, Yan-Fu
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Huang, Shih-Che
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Shih, Wei-Lun
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Tai, Ya-Hsiang
;
光電工程學系
The degradation of poly-Si TFT under different gate pulse waveforms is investigated. The mobility degradation is analyzed with the lateral transient electric field and carrier numbers near the channel edges. A proposed index fairly depicts the device degradation, which is helpful in evaluating lifetime for the poly-Si TFT circuits.
Estimation of the effect of channel shortening for P-type poly-Si TFTs under AC stress
(2007)
Huang, Shih-Che
;
Tsao, Hung-Chuan
;
Tai, Ya-Hsiang
;
光電工程學系
;
Department of Photonics
The behavior of the channel shortening effect of the P-type poly-Si TFTs under gate dynamic stress is examined with the I-V and C-V curves. It is discovered the effect is similar to the HEIP effect in P-MOSFETs. The affected channel length estimated from C-V curves is also in accordance with the increased mobility extracted from the I-V curves.
Generalized Hot-Carrier Degradation and Its Mechanism in Poly-Si TFTs Under DC/AC Operations
(2011-03-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Chen, Po-Ting
;
Lin, Chih-Jung
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光電工程學系
In the previous report, we had reported the mechanism for the degradation of poly-Si TFTs under OFF region gate ac operation with the source and drain electrodes grounded. In this paper, the study is extended to the degradation of the devices under various ac and dc operation conditions. It is discovered that, though these stress conditions are different, the corresponding degradation behaviors in their I-V and C-V curves all resemble the degradation behavior of the device under dc hot-carrier stress. Two important factors, namely, the electric field across the junction and the number of carriers flowing through the junction, are taken into discussion in this paper and comparison of these stress conditions. It is then categorized that these operation conditions can be described as the "generalized hot-carrier effect," since the degradation is found to occur near the junctions by the energized carriers, just as that under dc hot-carrier stress. The qualitative comparison of the electric field and carrier flow through the junction for the four stress conditions as well as the difference in the degradation mechanism between MOSFETS and poly-Si TFTs are also provided.
Statistical study on the states in the low-temperature poly-silicon films with thin film transistors
(2006-11-25)
Huang, Shih-Che
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Chou, Yen-Pang
;
Tai, Ya-Hsiang
;
光電工程學系
;
顯示科技研究所
Laser recrystallized low temperature poly-silicon films have attracted attention for their applications in thin-film transistors (TFTs), which are widely used in active matrix displays. The electrical characteristics of the poly-silicon film may vary because of its grain boundaries. In this work, the variation is statistically studied with respect to the threshold voltage and mobility of the TFTs. The threshold voltage and mobility of many closely-located TFTs are measured. These two parameters correspond to the deep states and tail states of the poly-silicon film, respectively. The mutual difference of two threshold voltages exhibits the distribution in a Gaussian-Lorentzian cross product form. On the other hand, the mutual difference of two mobility exhibits the distribution of Lorentzian function. This result directly reflects the local fluctuations and the spatial trends of the deep and tail states in a poly-silicon film. (c) 2006 Elsevier B.V. All rights reserved.
Study on electrical degradation of p-type low-temperature polycrystalline silicon thin film transistors with C-V measurement analysis
(2006-11-25)
Huang, Shih-Che
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Kao, Yu-Han
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Tai, Ya-Hsiang
;
光電工程學系
;
顯示科技研究所
Laser recrystallized low-temperature poly-silicon (LTPS) films have attracted attention for their application in thin-film transistors (TFTs), which are widely used in active matrix display. However, the degradation behavior of p-type LTPS TFTs is not quite clarified yet. In this paper, the instability mechanisms of p-channel LTPS TFTs under DC bias stress have been investigated. From the IV transfer curves, it was observed that LTPS TFT's mobility increases after stress at some bias conditions. This degradation is most likely caused by interface traps between the poly-Si thin film and the gate insulator, as well as the damaged junction of the drain from stress. In this work, the assumption is examined via C-V measurement. It is found that the C-GD curves of the stressed TFT slightly increase for the gate voltage smaller than the flat band voltage V-FB. However, the C-Gs curves of the stressed device are almost the same as those before stress. By employing simulation, it is found that the degradation of p-type TFTs under this stress condition is mainly caused by the trapped charges at the interface between the gate and the drain region, which is generated by the high voltage difference applied during DC bias stress. (c) 2006 Elsevier B.V. All rights reserved.
The Linear Combination Model for the Degradation of Amorphous Silicon Thin Film Transistors under Drain AC Stress
(2008-08-01)
Tai, Ya Hsiang
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Tsai, Ming-Hsien
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Huang, Shih-Che
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工學院
;
光電工程學系
The degradation behavior of hydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) under steady-state (DC) and pulsed (AC) stress on drain electrode has been investigated in this paper. Signals with various peak levels, frequencies and duty ratios are applied onto the drain electrode to see their effects on device's reliability. The effects of state creation and removal are found to still be the dominant degradation mechanisms of drain stress. With the experiment data, it is significantly proved that the degradation behavior can be predicted by analyzing the gate-to-source and gate-to-drain vertical electric field during stress. Furthermore. a linear combination model has been contributed in this paper. By using this model, one can estimate the threshold volta, e shift under drain AC stress of different voltage levels, frequencies, duty ratios for a given stress time. With satisfactory agreement between the real and estimated data, this model has been proved to be very useful in predicting and evaluating a-Si:H TFT reliability with both gate and drain signal applied.
Variation and mismatch effects of the low-temperature poly-Si TFTs on the circuit for the X-ray active matrix sensor
(2008-05-01)
Tai, Ya-Hsiang
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Huang, Shih-Che
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Su, Ko-Ching
;
Tseng, Chen-Yeh
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顯示科技研究所
The application of the capability of low-temperature poly-Si TFT circuits for high resolution X-ray active matrix sensor is explored. The integration of poly-Si TIFT circuits oil the glass enables an easy connection for the sensor array with fine pixel pitch. A novel charge sensitive amplifier circuit employing poly-Si TFTs is proposed for the readout system of the active matrix sensor. It can considerably increase the circuit's immunity to the unavoidable threshold voltage variations of the poly-Si TFTs.. The V-TH mismatch effect of the TFTs, which results in the offset voltage of the charge amplifier, can also be suppressed by the proposed circuit. However, the noise arisen from the V-TH mismatch can be even larger than that from the V-TH variation after compensation. It reflects that, for higher bit digital X-ray image sensors, the mismatch effect of the devices must be properly taken into consideration. (c) 2007 Elsevier Ltd. All rights reserved.