Degradation of the capacitance-voltage behaviors of the low-temperature polysilicon TFTs under DC stress

Abstract

In this paper, the degradation of n-type low-temperature polycrystalline silicon (poly-Si) thin-film transistors (TFTs) under dc stress is investigated with measurement of the capacitance between the source and the gate (C-GS), as well as the capacitance between the drain and the gate (C-GD). It is discovered that the degradation in C-GD curves of the device after hot carrier stress shows apparent frequency dependence, while that in the C-GS curves remains almost the same. A circuit model based on the channel resistance extracted from the current-voltage behavior is proposed to describe the frequency dependence of the capacitance behavior. From this model, it is revealed that the anomalous frequency-dependent capacitance-voltage characteristics may simply reflect the transient behaviors of the channel resistances. Besides, it was found that the C-GS curves after self-heating effect exhibit a significant shift in the positive direction and an additional increase for the smaller gate voltage, while the C-GD curves show only positive shifts. By employing simulation, it was proved that the self-heating effect creates interface states near the source region and increases the deep states in the poly-Si film near drain. The proposed circuit model further explains the behavior of the C-GS and C-GD curves for the stressed device at different measuring frequencies. (C) 2007 The Electrochemical Society.