Browsing by Author "Jiang, HC"

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A 2-D velocity- and direction-selective sensor with BJT-based silicon retina and temporal zero-crossing detector
(1999-02-01)
Jiang, HC
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 2-D velocity- and direction-selective visual motion sensor with a bipolar junction transistor (BJT)-based silicon retina and temporal zero-crossing detector is proposed and implemented. In the proposed sensor, a token-based delay-and-correlate computational algorithm is adopted to detect the selected speed and direction of moving object images. Moreover, binary pulsed signals are used as correlative signals to increase the velocity and direction selectivities, Each basic detection cell in the sensor has a compact architecture, which consists of one BJT-based silicon retina cell, one current-input edge extractor, two delay paths, and four correlators, Using the proposed architecture, an experimental 32 x 32 visual motion sensor chip with a cell size of 100 x 100 mu m(2) has been designed and fabricated by using 0.6-mu m CMOS technology. The correct operations of the fabricated sensor chip have been verified through measurements. The measured ranges of selectively detected velocity and direction in the fabricated sensor chip are 56 mm/s-5 m/s and 0-360 degrees, respectively. The complete sensor system consumes 20 mW at 5 V.
Active device under bond pad to save I/O layout for high-pin-count SOC
(2003-01-01)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To save layout area for electrostatic discharge (ESD) protection design in the SOC era, test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-mum one-poly-four-metal (1P4M) 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the effect of bonding stress on the active devices under the pads. Threshold voltage, off-state drain current, and gate leakage current of these devices under bond pads have been measured. After assembled in wire bond package, the measurement results show that there are only little variations between devices under bond pads and devices beside bond pads. This result can be applied on saving layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count system-on-a-chip (SOC).
An improved BJT-based silicon retina with tunable image smoothing capability
(1999-06-01)
Wu, CY
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An improved bipolar junction transistor (BJT) based silicon retina with simple and compact structure is proposed and analyzed, In the proposed structure, the BJT smoothing network, which models the layer of horizontal cells in the vertebrate retina, is implemented by placing enhancement n-channel MOSFET's among the bases of parasitic BJT's existing in a CMOS process to form an unique and compact structure. Thus, the smoothing characteristics can be tuned in a wide range. Moreover, an extra emitter is incorporated with each BJT at the pixel to act as the row switch. This reduces the cell area of the silicon retina and increases the resolution. Using the proposed new structure, an experimental 64 x 64 BJT-based silicon retina chip has been fabricated by using 0.5-mu m CMOS technology. The measurement results on the tunability of the smooth area in the smoothing network as well as the dynamic characteristics of the proposed silicon retina in detecting moving objects have been presented. It is believed that the improved structure is very suitable for the very large scale integration implementation of the retina and its application systems for CMOS smart sensors.
Automatic methodology for placing the guard rings into chip layout to prevent latchup in CMOS IC's
(2001)
Ker, MD
;
Jiang, HC
;
Peng, JJ
;
Shieh, TL
;
電子工程學系及電子研究所
A program methodology is proposed to automatically place the guard rings in the chip layout to improve latchup immunity of the CMOS IC's. The additional guard rings between the I/O cells and the internal circuits had been practically proven to significantly increase the latchup immunity of CMOS IC's. Therefore, the layout spacing from the I/O cells to the internal circuits can be reduced to a reasonable distance to save the total chip size. In this paper, a "Guard Ring Automation" program to realize the additional guard rings in the layout is proposed to make the layout more automatically and accurately.
Design of low-capacitance bond pad for high-frequency I/O applications in CMOS integrated circuits
(2000)
Ker, MD
;
Jiang, HC
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new structure of bond pad is proposed to reduce its parasitic capacitance in a baseline CMOS process without any process modification. The proposed bond pad has a capacitance less than 50% of that in the traditional bond pad. In addition, this new bond pad also provides better bonding adhesion of 10% improvement than the traditional one. It is greatly useful for high-frequency IC's, which need a very low input capacitance.
Design of negative charge pump circuit with polysilicon diodes in a 0.25-mu m CMOS process
(2002)
Ker, MD
;
Chang, CY
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A charge pump circuit realized with the substrate-isolated polysilicon diode in the 0.25-mum CMOS process is proposed. With the polysilicon diode, the stable negative voltage generation can be realized in general sub-quarter-micron CMOS process without extra process modification or additional mask layer. The device characteristic of polysilicon diode and the voltage waveforms of the negative charge pump circuit have been successfully verified in a 0.25-mum CMOS process with grounded p-type substrate.
Design on the low-capacitance bond pad for high-frequency I/O circuits in CMOS technology
(2001-12-01)
Ker, MD
;
Jiang, HC
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new structure design of bond pad is proposed to reduce its parasitic capacitance in general CMOS processes without extra process modification. The proposed bond pad is constructed by connecting multilayer metals and inserting additional diffusion layers into the substrate below the metal layers. The metal layers except top metal layer are designed with special patterns, which have smaller area than that in the traditional bond pad. Both the additional diffusion layers and patterned metal layers are used to reduce the parasitic capacitance of bond pad. An experimental test chip has been designed and fabricated to investigate the reduction of parasitic capacitance of the bond pad. The bonding reliability tests on the fabricated bond pad, including the ball-shear and wire-pull tests, are also used to verify the bonding adhesion. The experimental results show that the proposed low-capacitance bond pad has a capacitance less than 50% of that in the traditional bond pad. The new proposed bond pads can also keep the same good bonding reliability as that of a traditional bond pad.
ESD test methods on integrated circuits: An overview
(2001)
Ker, MD
;
Peng, JH
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
ESD phenomenon has become a serious problem for IC products fabricated by deep-submicron CMOS technologies. To qualify the ESD immunity of IC products, there are some test methods and standards developed by some organizations, which are ESDA, AEC, EIA/JEDEC, and MIL-STD organizations. ESD events have been classified into 4 models, which are HBM, MM, CDM, and SDM. Besides, there are 4 modes of pin combinations for ESD zapping on the IC pins, which are specified as (1) Pin-to-VSS, (2) Pin-to-VDD, (3) Pin-to-Pin, and (4) VDD-to-VSS. All the test methods are designed to evaluate the ESD immunity of IC products. The zap number, zap interval, and sample size are all well defined in the related industrial standards. This paper provides an over-view among ESD test methods on IC products. In general, the commercial IC products are requested to sustain at least 2-kV HBM, 200-V MM, and 1-kV CDM ESD stresses.
Failure analysis of ESD damage in a high-voltage driver IC and the effective ESD protection solution
(2002)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電機學院
;
College of Electrical and Computer Engineering
In the blink of a silicon eye
(2001-05-01)
Cheng, CH
;
Wu, CY
;
Sheu, B
;
Lin, LJ
;
Huang, KH
Latchup current self-stop circuit for whole-chip latchup prevention in bulk CMOS integrated circuits
(2002)
Peng, JJ
;
Ker, MD
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A latchup current self-stop methodology and circuit design, which are used to prevent damage in the bulk CMOS integrated circuits due to latchup, are proposed in this paper. In a bulk CMOS chip, the core circuit blocks are always latchup sensitive due to a low holding voltage of the parasitic SCR path. The proposed latchup prevention methodology and circuit design can detect and stop the occurrence of latchup without any process modification or extra fabrication cost. It is suitable for whole-chip latchup prevention of bulk CMOS integrated circuits. This proposed latchup current self-stop methodology and circuit have been verified in a 0.5-mum 1P3M bulk CMOS process.
Test structure and verification on the MOSFET under bond pad for area-efficient I/O layout in high-pin-count SOCIC's
(2003)
Ker, MD
;
Peng, JJ
;
Jiang, HC
;
電機學院
;
College of Electrical and Computer Engineering
For saving the layout area of I/O cells in SOC chips, a test chip with large size NMOS devices placed under bond pads has been fabricated in 0.35-mum 1P4M 3.3V CMOS process for verification. The bond pads had been drawn with different layout patterns on the inter-layer metals to investigate the impact of bonding stress on the active devices under the pads. The measurement results, including thermal shock and temperature cycling tests, show that there are only little variations between devices under bond pads and devices beside bond pads. This discovery can be applied to save layout area for on-chip ESD protection devices or I/O devices of IC products, especially for the high-pin-count SOC IC's.
The BJT-based silicon-retina sensory system for direction- and velocity-selective sensing
(1998)
Jiang, HC
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a BJT-based silicon-retina sensory system for direction- and velocity-selective sensing is proposed and implemented. This detector can selectively detect the specified direction and speed of moving object image in 2-dimension. The basic detection cell consists of one BJT-based silicon retina cell, one current-mode edge extractor, two delay paths, and four correlators. The signals which are used to be correlated are binary pulsed signals. The BJT-based silicon retina with the current-mode edge extractor can be easily incorporated into various motion measurement systems and associated image processing neural network to reduce the hardware complexity for VLSI implementations and provide robust edge detection. Using the proposed architecture, an experimental 2-D 32x32 motion measurement chip has been fabricated by using 0.6 mu m CMOS technology. The functions of the proposed sensory system are also verified through measurements.
Whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology
(2001)
Ker, MD
;
Jiang, HC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On-chip : electrostatic discharge (ESD) protection circuits had been built in IC chips to protect the devices and circuits against ESD damage. But, ESD protection circuits constructed with the scaled-down CMOS devices are very weak to ESD stress. Therefore, novel ESD protection solutions must be developed to overcome this reliability challenge for integrated circuits fabricated in the nano-scale CMOS technology. In this paper, the whole-chip ESD protection strategy for CMOS integrated circuits in nanotechnology has been proposed with two main methods. One is the substrate-triggered circuit technique used to effectively improve ESD robustness of devices in the nano-scale CMOS technology. The other is the novel design concept of "ESD Buses" used to solve the internal ESD damage issue of CMOS IC with multiple and separated power lines. The internal circuits or interface circuits, realized by nano-scale CMOS devices, are more sensitive to such internal ESD damage issue. By using ESD buses, ESD current can be quickly discharged far away from the internal circuits or interface circuits of CMOS IC to achieve the goal of whole-chip ESD protection.