Browsing by Author "Kao, Kuo-Hsing"

Now showing 1 - 20 of 22

Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
Demonstration of Annealing-free Metal-Insulator-Semiconductor (MIS) Ohmic Contacts on a GaN Substrate using Low Work-function Metal Ytterbium (Yb) and Al2O3 Interfacial Layer
(2019-01-01)
Wu, Tian-Li
;
Tseng, Yang-Yan
;
Huang, Chih-Fang
;
Chen, Zih-Sin
;
Lin, Chih-Chien
In this letter, the Metal-Insulator-Semiconductor (MIS) contacts are fabricated on the GaN substrates and compared to the Metal-Semiconductor (MS) contacts. To alleviate the Fermi level pinning effect at the Metal-Semiconductor interface, an Al2O3 interfacial layer (IL) (1 similar to 3 nm) is used to form the MIS contacts. By comparing the electrical characteristics, the contact with Onm Al2O3 layer, i.e., MS contact, shows a lowest current compared to the contacts with an Al2O3 IL, i.e., MIS contact. Furthermore, the current at 0.5V in the fabricated Transmission Line Measurement (TLM) device with lnm Al2O3 IL is 10(3) times higher the one without an Al2O3 IL. This proves that inserting an Al2O3 IL could mitigate the Fermi level pinning, resulting in a low Schottky barrier height. Finally, based on the TLM analysis, the resistivity of 5.1x10(-4) Omega.cm(2) is demonstrated in the MIS contact with lnm Al2O3 IL.
Diamond-shaped Ge and Ge0.9Si0.1 Gate-All-Around Nanowire FETs with Four {111} Facets by Dry Etch Technology
(2015)
Lee, Yao-Jen
;
Hou, Fu-Ju
;
Chuang, Shang-Shiun
;
Hsueh, Fu-Kuo
;
Kao, Kuo-Hsing
We propose a feasible pathway to scale the Ge MOSFET technology by using a novel diamond-shaped Ge and Ge0.9Si0.1 gate-all-around (GAA) nanowire (NW) FETs with four {111} facets. The device fabrication requires only simple top-down dry etching and blanket Ge epitaxy techniques readily available in mass production. The proposed dry etching process involves three isotropic/anisotropic etching steps with different Cl-2/HBr ratios for forming the suspended diamond-shaped channel. Taking advantages of the GAA configuration, favorable carrier mobility of the {111} surface, nearly defect-free suspended channel, and improved dopant activation by incorporating Si, nFET and pFET with excellent performance have been demonstrated, including an I-on/I-off ratio exceeding 10(8), the highest ever reported for Ge-based pFETs.
Fabrication of Vertically Stacked Nanosheet Junctionless Field-Effect Transistors and Applications for the CMOS and CFET Inverters
(2020-09-01)
Sung, Po-Jung
;
Chang, Shu-Wei
;
Kao, Kuo-Hsing
;
Wu, Chien-Ting
;
Su, Chun-Jung
In this study, conventional CMOS and complementary field-effect transistor (CFET) inverters based on a vertically stacked-nanosheet (NS) structure were fabricated. The NS below 8-nm channel layer thickness (T-Si) was obtained by dry etching and wet etching processes. The channel thickness is controlled by dry etching, and the channel width was shrunk down by wet etching. Compared to single nanowire field-effect transistors (NSFETs), stacked NSFETs exhibit higher ON-current performance. For the CMOS inverter, the voltage transfer characteristics (VTCs) could be matched much better by adjusting the channel widths and layers for N-channel MOSFET (NFET) and P-channel MOSFET (PFET), respectively. For the CFET inverter, layout areas could be reduced and requires less number of lithographic and ion implantation steps contrary to the CMOS inverter. However, we observe that the VTCs of the CFET inverters still show asymmetric behavior due to the difficulties of adjustment in NS layers and systematic behavior of threshold voltages for NFETs/PFETs. This work experimentally demonstrates the CMOS and CFET inverters on the vertically stacked NS structure, which is promising for system-on-panel (SoP) and 3-D-ICs applications.
Fluorinated HfO2 Gate Dielectrics Engineering for CMOS by pre- and post-CF4 Plasma Passivation
(2008)
Wu, Woei-Chemg
;
Lai, Chao-Sung
;
Lee, Shih-Ching
;
Ma, Ming-Wen
;
Chao, Tien-Sheng
In this paper, we demonstrate TaN/Fluorinated HfO2 CMOS devices, focusing on symmetry and asymmetry fluorine incorporation at top or bottom HfO2 interfaces. 16% permittivity enhancement, 65% and 91% mobility increases for electron and hole, respectively, under high electric field was achieved. Reliability of n- and p-MOSFET was improved 3 orders and 8% for GIDL and hot carrier immunity, respectively. A physical model of shallow and deep trapping level affected by fluorine was proposed to explain the NBTI and PBTI improvements.
Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices
(2006-09-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Kao, Kuo-Hsing
;
Huang, Jyun-Siang
;
Lei, Tan-Fu
In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metaloxide-semiconductor field-effect transistor (MOSFET) with high-kappa gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-kappa offset spacer to further improve the on-state driving current I-on to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current I-off by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-kappa material as a spacer. This enhanced fringing electric field can markedly increase I-on/I-off current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.
High Performance Poly Si Junctionless Transistors with Sub-5nm Conformally Doped Layers by Molecular Monolayer Doping and Microwave Incorporating CO2 Laser Annealing for 3D Stacked ICs Applications
(2015)
Lee, Yao-Jen
;
Cho, Ta-Chun
;
Sung, Po-Jung
;
Kao, Kuo-Hsing
;
Hsueh, Fu-Kuo
A junctionless (JL) fin thin film transistor (FinTFT) with a novel shell doping profile (SDP) formed by a damage-free conformal molecular monolayer doping (MLD) method and a combination of microwave annealing (MWA) and CO2 laser spike annealing (COLSA) is demonstrated and studied. MWA drives in and partially activates the MLD dopants; the resultant SDP features an ultra-shallow depth (< 5nm) and an abrupt steepness (< 0.8 nm/dec). The dopant activation of the devices experienced MLD and MWA is further enhanced by the nonmelting COLSA without dopant diffusion, and which can also avoid fin deformation and recover surface defects left by fin patterning. Thanks to the enhanced dopant activation by COLSA, the SDP-FinTFTs overall exhibit better performance than the SDP-FinTFTs without COLSA and the conventional implanted (imp) FinTFTs in terms of subthreshold swing (S.S.), on-currents (I-on by 160% compared to the SDP-FinTFTs without COLSA) and on/off current ratio (I-on/I-off > 10(7)) for 3D stacked ICs applications. Our results reveal the potential of the proposed SDP formed by MLD, MWA and COLSA enabling a JLFinTFT showing excellent performance.
High-kappa material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications
(2006-11-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Kao, Kuo-Hsing
;
Huang, Jyun-Siang
;
Lei, Tan-Fu
In this paper, fully depleted silicon-on-insulator (SOI) devices with source/drain extension shifts and a high-kappa offset spacers were investigated in detail. The calculated results show that the source/drain extension shift can decrease off-state leakage current I-off significantly by utilizing the extra electron barrier height in the source/drain extension shift region to reduce standby power dissipation. However, the on-state driving current In is also sacrificed simultaneously. To overcome this drawback, a high-kappa offset spacer is used to increase the on-state driving current I-on effectively by enhancing the vertical fringing electric field which elevates the channel voltage drop and reduces series resistance.
High-performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure
(2008-06-01)
Ma, Ming-Wen
;
Chao, Tien-Sheng
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Kao, Kuo-Hsing
In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral-crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage V-TH similar to 0.095 V, excellent subthreshold swing S.S. similar to 83 mV/dec., and high field-effect mobility mu(FE) similar to 240 cm(2)/V center dot s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 mn.
Impact of high-k offset spacer in 65-nm node SOI devices
(2007-03-01)
Ma, Ming-Wen
;
Wu, Chien-Hung
;
Yang, Tsung-Yu
;
Kao, Kuo-Hsing
;
Wu, Woei-Cherng
In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
Impact of the polarization on time-dependent dielectric breakdown in ferroelectric Hf0.5Zr0.5O2 on Ge substrates
(2020-04-01)
Yang, Ting-Hsin
;
Su, Chun-Jung
;
Wang, Yu-Shun
;
Kao, Kuo-Hsing
;
Lee, Yao-Jen
In this work, polarization-dependent time-dependent dielectric breakdown in ferroelectric HZO Ge MOSCAPs presented. First, ferroelectric HZO Ge MOSCAPs with and without in-situ NH3 plasma interfacial layer, treatment exhibit the two distinct remnant polarization (P-r), Secondly the device with a larger P-r shows a higher gate leakage current and smaller time-to-breakdown (t(BD)) compared to the device with a smaller P-r. Then, a physical model based on the high probability of the electron tunneling accelerating the formation of the percolation path is proposed. Finally, the device with large P-r shows a lower extrapolated operating voltage. However more than 1.5 V of the extracted operation voltage for 1% failure of 10 year lifetime in the device with large P-r still can be obtained. (C) 2020 The Japan Society of Applied Physics
Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
(2008-02-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Wu, Yi-Hong
In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
Impacts of nitric acid oxidation on low-temperature polycrystalline silicon TFTs with high-k gate dielectric
(2007)
Yang, Tsung-Yu
;
Ma, Ming-Wen
;
Kao, Kuo-Hsing
;
Su, Chun-Jung
;
Chao, Tien-Sheng
In this paper, low-temperature polycrystalline-silicon thin-film transistors (LTPS-TFrs) with HfO2 gate dielectric and nitric acid oxidation pre-treatment is investigated. Significant improvement on on/off current ratio and field effect mobility is observed due to the nitric acid oxidation pre-treatment. An excellent on/off current ratio and subthreshold swing, as well as low threshold voltage and I-off can be achieved without any other hydrogen passivation treatments. These improved performances can be attributed to both the high gate capacitance density using high-k gate dielectric and the good interface quality by nitric acid oxidation of poly-silicon.
Impacts of the Shell Doping Profile on the Electrical Characteristics of Junctionless FETs
(2015-11-01)
Kumar, Malkundi Puttaveerappa Vijay
;
Hu, Chia-Ying
;
Kao, Kuo-Hsing
;
Lee, Yao-Jen
;
Chao, Tien-Sheng
This paper presents the impacts of an advanced shell doping profile (SDP) on the electrical characteristics of a junctionless (JL) FET in terms of OFF-current, subthreshold swing (SS), and ON-current by a numerical simulator. Due to the potential mirroring effect, a special observation stemming from the SDP, the carriers can enter the intrinsic region from the doped surface reducing the series resistance though the junction depth is smaller than 5 nm. The proposed doping profile provides an additional structure parameter for designing a JL FET showing the mitigated short-channel effects, a better SS, and a higher ON/OFF current ratio for sub-20-nm channel length. Compared with traditional devices, a JL FET with the proposed SDP shows a lower OFF-current by decades and less electrical characteristics variation caused by the nanowire diameter variation. The SDP not only reduces the series resistance of a JL FET but also poses a possible solution of avoiding the negative impacts of quantum confinement for advanced technology nodes.
Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation
(2008-03-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Su, Chun-Jung
;
Wu, Woei-Cherng
;
Yang, Tsung-Yu
In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I-on/I-min current ratio 1.9 x 10(6) are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO2/polysilicon interface. Significant improvements on subthreshold swing and I-min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage similar to 1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I-on/I-min current ratio 1.21 x 10(7), which is suitable for the application of system-on panel (SOP). (c) 2007 Elsevier Ltd. All rights reserved.
Improving the Electrical Performance of a Quantum Well FET With a Shell Doping Profile by Heterojunction Optimization
(2017-09-01)
Kumar, Malkundi Puttaveerappa Vijay
;
Hu, Chia-Ying
;
Walke, Amey Mahadev
;
Kao, Kuo-Hsing
;
Chao, Tien-Sheng
This paper investigates the impacts of typical semiconductor material properties-electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core-shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core-shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications.
Junctionless FETs With a Fin Body for Multi-V-TH and Dynamic Threshold Operation
(2018-08-01)
Kumar, Malkundi Puttaveerappa Vijay
;
Lin, Jer-Yi
;
Kao, Kuo-Hsing
;
Chao, Tien-Sheng
;
電子物理學系
In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+FB can control the electrostatic potential of the channel more efficiently for multi-V-TH (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor (gamma) is predicted for wide range V-TH modulation. Thanks to the stronger potential coupling between the channel and FB, the proposeddevice exhibits gamma improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi-V-TH operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption.
Mobility improvement of HfO2 LTPS-TFTs with nitrogen implanataion
(2007)
Ma, Ming-Wen
;
Yang, Tsung-Yu
;
Kao, Kuo-Hsing
;
Su, Chun-Jung
;
Chao, Tien-Sheng
In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFrs) with high-k HfO2 gate dielectric and nitrogen implantation to achieve high-performance characteristics for the first time. Various nitrogen does 5 X 10(13) and 5 X 10(14) cm(-2) were implanted after gate dielectric deposition. Significant improvement 94.4% and 74.4% on transconductance G(m) and field effect mobility, respectively, are observed due to the nitrogen implantation. In addition, a substantial gate leakage current reduction over four orders is also obtained to decrease undesirable power dissipation. Finally, a high performance LTPS-TFT with low subthreshold swing 0.177 V/decade and threshold voltage about 1 V can be achieved without any other hydrogen plasma passivation treatments.
Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI, and hot-carrier stress
(2008-05-01)
Ma, Ming-Wen
;
Chen, Chih-Yang
;
Wu, Woei-Cherrig
;
Su, Chun-Jung
;
Kao, Kuo-Hsing
In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with HfO2 gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the HfO2 gate dielectric is observed for the PBS and PBTI of the HfO2 LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the HfO2 LTPS-TFT.
Ultra-Shallow Junction Formation by Monolayer Doping Process in Single Crystalline Si and Ge for Future CMOS Devices
(2017-01-01)
Chuang, Shang-Shiun
;
Cho, Ta-Chun
;
Sung, Po-Jung
;
Kao, Kuo-Hsing
;
Chen, Henry J. H.
We focused on the damage-free monolayer doping (MLD) method starting from a chemical reaction of molecules on Si and Ge surfaces and applied it to 3D MOSFET device fabrication. MLD methods were verified by different material analysis, such as XPS and Raman spectroscopy. For a Si-based FinFET structure, compared to the device with ion implantation, the short channel effect of source and drain (SD) extension regions formed by MLD are improved. The shallower SD extension regions formed by low-temperature microwave annealing (MWA) are expected to the device showing better electrical properties than deeper ones formed by RTA. In addition, formation of the n- and p-type doping in Ge by MLD was also investigated. Even after annealing at 800 degrees C for 300 sec by RTA, the p-type doping still exhibits a low surface doping concentration due to the low diffusion coefficient of B in Ge and surface diffusion limitations at the MLD/Ge interface. By using a combination of RTA and CO2 laser spike annealing (LSA), MLD n-type doping in Ge are formed with junction depths of approximate to 15 nm, and peak concentration of approximate to 6 x 10(20) atoms/cm(3). The dopant activation for the MLD-doped channels of Ge junctionless FinFETs (JLFinFETs) is improved after the additional CO2 LSA. (C) 2017 The Electrochemical Society. All rights reserved.