Browsing by Author "LEE, CL"

Now showing 1 - 20 of 93

A COMPLEMENT-BASED FAST ALGORITHM TO GENERATE UNIVERSAL TEST SETS FOR MULTIOUTPUT FUNCTIONS
(1994-03-01)
CHEN, BY
;
LEE, CL
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a fast universal test set (UTS) generation algorithm for multi-output functions is presented. The algorithm first generates the UTS for single-output functions by directly Shannon-expanding and complementing the function. This significantly reduces the time complexity and the usage of temporary memory. Also, it stores tests in test cubes to save the size of memory for test storing. Two-six orders of magnitude in computation efficiency improvement and 1-1800 fold for memory saving over the conventional method are achieved. It then merges the generated test cubes for each single-output function into a set of mutually disjoint test cubes to be the UTS for a multi-output function by employing a new compaction technique. The size of UTS thus obtained is 1-20 times smaller than that of UTS without compaction.
A DOUBLE METAL STRUCTURE PT/AL/N-INP DIODE
(1995-07-01)
HUANG, WC
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LEI, TF
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LEE, CL
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A DOUBLE POLE, DOUBLE THROW ELECTRO-OPTIC SWITCH WITH AN N-TYPE ELECTRODE
(1980)
LEE, CL
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HUANG, JY
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
A PLANAR ELECTRO-OPTIC PRISM ARRAY BEAM SPLITTER
(1980)
HUANG, JY
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LEE, CL
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
A PLANAR ELECTROOPTIC BEAM SPLITTER WITH A ZIG-ZAG ELECTRODE
(1983)
LEE, CL
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HORNG, JS
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HUANG, CH
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奈米中心
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Nano Facility Center
A POLYSILICON-ON-OXIDE (POSOX) ISOLATION STRUCTURE FOR BIPOLAR INTEGRATED-CIRCUITS
(1987-08-01)
LEE, CL
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TAN, FL
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WU, NW
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TANG, RB
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交大名義發表
A REAL-TIME C-V MEASUREMENT CIRCUIT FOR MOS CAPACITORS UNDER CURRENT STRESSING
(1991-08-01)
LEE, CL
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LEI, TF
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HO, JH
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WANG, WT
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電子工程學系及電子研究所
A dynamic large signal C-V measurement circuit is presented to measure real time C-V characteristics of a MOS structure under current stressing conditions. The real time information on the generation and filling of traps and surface states can thus be obtained. With this circuit it has been shown that, for an Al-gate MOS structure, charges on traps and interface surface states recover immediately after the stressing is removed.
A STUDY OF THE INTERFACIAL LAYER OF AL AND AL(1-PERCENT SI)-SI CONTACTS USING A ZERO-LAYER ELLIPSOMETRY MODEL
(1992-11-01)
CHAO, TS
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LEE, CL
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LEI, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, the interfacial layer of the Al-Si and Al(1% Si) Si contacting system annealed at different temperatures have been studied using ellipsometry incorporated with a zero-layer model. The results show that the thickness of the interfacial P+ layer between Al or Al(1% Si) and the Si-substrate increases with the annealing temperature and the thickness of the P+-layer of the Al(1% Si)-Si system is generally lower than that of the Al-Si system. Also, the fraction of Al in the interfacial layer decreases with the annealing temperature for the Al-Si system, but increases for the Al(1% Si)-Si system. The electrical measurements show that the interface of the Al(1% Si)-Si contact is more stable than that of the Al-Si contact.
A SWITCHING DEVICE OF A PN JUNCTION STRUCTURE WITH 2 LAYERS OF THIN OXIDE
(1989-06-01)
CHANG, DCY
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LEE, CL
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LEI, TF
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交大名義發表
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電控工程研究所
A VERTICAL KELVIN TEST STRUCTURE FOR MEASURING THE TRUE SPECIFIC CONTACT RESISTIVITY
(1986-04-01)
LEI, TF
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LEU, LY
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LEE, CL
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交大名義發表
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電控工程研究所
ALGEBRAIC DIVISION FOR MULTILEVEL LOGIC SYNTHESIS OF MULTIVALUED LOGIC-CIRCUITS
(1994)
WANG, HM
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LEE, CL
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CHEN, JE
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
AN ANALYTICAL MODEL FOR THE ABOVE-THRESHOLD CHARACTERISTICS OF POLYSILICON THIN-FILM TRANSISTORS
(1995-07-01)
CHERN, HN
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LEE, CL
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LEI, TF
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An analytical model for the above-threshold characteristics of long-channel, small-grain and thin channel polysilicon thin film transistors (TFT's) is presented. This model is constructed by considering the barrier potential and the carrier trapping effect at grain boundaries of the channel. A band tail state located at E(c) - 0.15 eV is taken into account to simulate the I-V characteristics. Based on the model, the theoretically simulated results show good agreement with the experimental data of the plasma-passivated and unpassivated TFT devices in a wide range of the gate, drain biases and the temperature. The correlation of the transconductance to the gate bias is also investigated, It is found that the decrease of grain-boundary barrier potential with the gate voltage enhances the transconductance, while this enhancement effect becomes insignificant and causes the decrease of the transconductance at the high gate bias.
AN MINPIM STRUCTURE MIXING DEVICE
(1989-04-01)
CHANG, DCY
;
LEE, CL
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LEI, TF
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交大名義發表
;
電控工程研究所
AN SCR WITH SIMPLE MIS STRUCTURE
(1990-12-01)
CHANG, DCY
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LEE, CL
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LEI, TF
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電控工程研究所
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Institute of Electrical and Control Engineering
A device to work as an SCR with a simple MIS p-n Structure is proposed and demonstrated. It employs two junction diodes, with a thin oxide layer grown prior to metallization. This device can act as a triac when a bi-directional ac voltage is applied, while acts as an SCR when a bias voltage is applied to the N-substrate.
BINARY PARTITION ALGORITHMS AND VLSI ARCHITECTURES FOR MEDIAN AND RANK ORDER FILTERING
(1993-09-01)
LEE, CL
;
JEN, CW
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A class of selection algorithms by binary partition is very efficient for median and rank order filtering. A unified discussion of these algorithms is presented. Binary partition algorithms have better time-area complexity than sorting methods. Counting, firing, and updating are three basic steps. A generic structure is proposed to realize these algorithms. They can be implemented by simple and regular modules in VLSI.
BIT-SLICED MEDIAN FILTER DESIGN BASED ON MAJORITY GATE
(1992-02-01)
LEE, CL
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JEN, CW
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
There are arithmetic problems for the hardware realisation of bit-level median filtering algorithms. A design of a majority gate which is composed of output-wired inverters is proposed. The area and time complexities are better than the digital and analogue designs now available. This circuit is applied to a median filter design which is based on majority selection, the computation problems are thus avoided. It is a bit-sliced architecture with constant cycle time. Window shapes can be arbitrarily changed through mask-and-set modules. A median filtering system for two-dimensional image processing is presented. A binary majority gate is also an essential element in decision-making circuitry which is applied in fault-tolerant computing systems, artificial neural networks or related applications.
CF4 PLASMA-ETCHING ON LINBO3
(1979)
LEE, CL
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LU, CL
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交大名義發表
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電控工程研究所
;
National Chiao Tung University
CHARACTERISTICS OF POLYSILICON CONTACTED SHALLOW JUNCTION DIODE FORMED WITH A STACKED-AMORPHOUS-SILICON FILM
(1993-10-01)
WU, SL
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LEE, CL
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LEI, TF
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CHANG, HC
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電子工程學系及電子研究所
A high-performance shallow junction diode formed with a stacked-amorphous-silicon (SAS) film is presented. Since the boundaries of stacked silicon layers and the poly/mono silicon interface act as a diffusion barrier for implanted dopants, the junction depth of SAS emitter contacted diode is about 500 angstrom shallower than that of the as-deposited polysilicon (ADP) emitter contacted diode. The fabricated SAS emitter contacted diodes exhibited a very low reverse leakage current (less-than-or-equal-to 1 nA/cm2 at -5 V) and a forward.ideality factor m almost-equal-to 1.001 over 7 decades on a log scale. The reverse I-V characteristics were found to be nearly independent of the reverse voltage from the room temperature to 200-degrees-C, and it was also found that the leakage current was due almost completely to the diffusion current. The plots of the diode leakage current versus the perimeter to area ratio showed that the periphery generation current only contributed a small portion to the total leakage. The processing temperature for the SAS emitter contacted p+-n diode can be as low as 600-degrees-C.
CHARACTERISTICS OF TOP-GATE THIN-FILM TRANSISTORS FABRICATED ON NITROGEN-IMPLANTED POLYSILICON FILMS
(1995-12-01)
YANG, CK
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LEI, TF
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LEE, CL
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The electrical characteristics of top-gate thin-film transistors (TFT's) fabricated on the nitrogen-implanted polysilicon of the doses ranging from 2 x 10(12)-2 x 10(14) ions/cm(2) were investigated in this work, The experimental results showed that nitrogen implanted into polysilicon followed by an 850 degrees C 1 h annealing step had some passivation effect and this effect was much enhanced by a following H-2-plasma treatment. The threshold voltages, subthreshold swings, ON-OFF current ratios, and field effect mobilities of both n-channel and p-channel TFT's were all improved, Moreover, the hot-carrier reliability was also improved, A donor effect of the nitrogen in polysilicon was also found which affected the overall passivation effect on the p-channel TFT's.
CHARACTERIZATION OF SEMIINSULATING POLYCRYSTALLINE SILICON PREPARED BY LOW-PRESSURE CHEMICAL-VAPOR-DEPOSITION
(1993-09-01)
CHAO, TS
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LEE, CL
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LEI, TF
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電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We employed the multiple angle incident ellipsometer to study the growth mechanism and optical properties of semi-insulating polycrystalline silicon (SIPOS) films deposited by the low-pressure chemical vapor deposition (LPCVD) technique. A significant difference of the imaginary part of the refractive index between film at the edge and those in the central region of the wafer was observed. Our analyses showed that it was consistent with the N2O depletion model. This N2O depletion phenomenon was confirmed by Auger analysis. Moreover, we found that spatial N2O depletion at the edge of the wafer was greatly influenced by the flow rate of SiH4 to N2O gases. Excessively high N2O flow rate suppressed the silicon microcrystal resulting in a thinner SIPOS film.